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  ON Semiconductor Electronic Components Datasheet  

NB3M8T3910G Datasheet

2.5V/3.3V 3:1:10 Configurable Differential Clock Fanout Buffer

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NB3M8T3910G pdf
NB3M8T3910G
2.5V/3.3V 3:1:10
Configurable Differential
Clock Fanout Buffer with
LVCMOS Reference Output
Description
The NB3M8T3910G is a 3:1:10 Clock fanout buffer operating on a
2.5 V/3.3 V Core VDD and a flexible 2.5 V / 3.3 V VDDO supply
(VDDO VDD).
A 3:1 MUX selects between Crystal oscillator inputs, or either of
two differential Clock inputs capable of accepting LVPECL, LVDS,
HCSL, or SSTL levels. The MUX select lines, SEL0 and SEL1, accept
LVCMOS or LVTTL levels and select input per Table 3. The Crystal
input is disabled when a Clock input is selected.
Differential Outputs consist of two banks of five differential outputs
with each bank independently mode configurable as LVPECL, LVDS
or HCSL. Each bank of differential output pairs is configured with a
pair of SMODEAx/Bx select lines using LVCMOS or LVTTL levels
per Table 6. Clock input levels and outputs states are determined per
Table 5.
The Single−Ended LVCMOS Output, REFOUT, is synchronously
enabled by the OE_SE control line per Table 4 using LVCMOS /
LVTTL levels. For Clock frequencies above 250 MHz, the REFOUT
line should be disabled.
www.onsemi.com
MARKING
DIAGRAM
1
1 48
QFN48
G SUFFIX
CASE 485AJ
NB3M8T
3910G
AWLYYWWG
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information on page 19 of
this data sheet.
Features
Crystal, Single−Ended or Differential Input Reference
Clocks
Differential Input Pair can Accept: LVPECL, LVDS,
HCSL, SSTL
Two Output Banks: Each has Five Differential Outputs
Configurable as LVPECL, LVDS, or HCSL by
SMODEAx/Bx Pins
One Single−Ended LVCMOS Output with Synchronous
OE Control
LVCMOS/LVTTL Interface Levels for all Control
Inputs
Clock Frequency: Up to 1400 MHz, Typical
Output Skew: 50 ps (Max)
Additive RMS Jitter <0.03 ps (156.25 MHz, Typical)
Input to Output Propagation Delay (900 ps Typical)
Operating Supply Modes VDD/VDDO: 2.5 V/2.5 V,
3.3 V/3.3 V or 3.3 V/2.5 V
Industrial Temperature Range −40°C to 85°C
This is a Pb−Free Device
Applications
Clock Distribution
Telecom
Networking
Backplane
High End Computing
Wireless and Wired Infrastructure
End Products
Servers
Ethernet Switch/Routers
ATE
Test and Measurement
© Semiconductor Components Industries, LLC, 2016
March, 2016 − Rev. 2
1
Publication Order Number:
NB3M8T3910/D


  ON Semiconductor Electronic Components Datasheet  

NB3M8T3910G Datasheet

2.5V/3.3V 3:1:10 Configurable Differential Clock Fanout Buffer

No Preview Available !

NB3M8T3910G pdf
VDD
GND
BANK A
SMODEA0
SMODEA1
SEL0
SEL1
CLK0
CLK0
CLK1
CLK1
XTAL_IN
XTAL_OUT
IREF
SMODEB0
SMODEB1
CONTROL
3:1
Mux
OSC
CONTROL
BANK B
OE_SE
SYNC
Figure 1. Simplified Logic Diagram
NB3M8T3910G
VDDOA
QA0
QA0
QA1
QA1
QA2
QA2
QA3
QA3
QA4
QA4
QB0
QB0
QB1
QB1
QB2
QB2
QB3
QB3
QB4
QB4
Exposed
Pad (EP)
QA0 1
QA0 2
QA1 3
QA1 4
VDDOA 5
QA2 6
QA2 7
VDDOA 8
QA3 9
QA3 10
QA4 11
QA4 12
48 47 46 45 44 43 42 41 40 39 38 37
NB3M8T3910G
13 14 15 16 17 18 19 20 21 22 23 24
36 QB0
35 QB0
34 QB1
33 QB1
32 VDDOB
31 QB2
30 QB2
29 VDDOB
28 QB3
27 QB3
26 QB4
25 QB4
VDDOB
VDDOC
REFOUT
Figure 2. QFN−48 Pinout Configuration
(Top View)
Table 1. PIN DESCRIPTION
Number
1, 2
3, 4
5, 8
Name
QA0, QA0
QA1, QA1
VDDOA
Type
Output
Output
Power
29, 32
VDDOB
Power
45
VDDOC
Power
6,7
9,10
11,12
13, 18,
24, 37,
43, 48
14, 47
QA2, QA2
QA3, QA3
QA4, QA4
GND
Output
Output
Output
Power
SMODEA0 /
SMODEA1
Input
Default
(Internal
Resistors)
Pulldown
Description
Bank A differential output pair Q0. Configurable as LVPECL / LVDS / HCSL
Bank A differential output pair Q1. Configurable as LVPECL / LVDS / HCSL
VDDOA Positive Supply pin for Bank A outputs. VDDOA pins must all be
externally connected to a power supply to guarantee proper operation.
Bypass with 0.01 mF cap to GND
VDDOB Positive Supply pin for Bank B outputs. VDDOB pins must all be
externally connected to a power supply to guarantee proper operation.
Bypass with 0.01 mF cap to GND
VDDOC Positive Supply pin for REFOUT output. VDDOC pin must be
externally connected to a power supply to guarantee proper operation.
Bypass with 0.01 mF cap to GND
Bank A differential output pair Q2. Configurable as LVPECL / LVDS / HCSL.
Bank A differential output pair Q3. Configurable as LVPECL / LVDS / HCSL
Bank A differential output pair Q4. Configurable as LVPECL / LVDS / HCSL
Ground Supply. All GND pins must be externally connected to power supply
to guarantee proper operation.
Output driver selectors for BANK A. See Table 6 for function.
LVCMOS/LVTTL levels.
www.onsemi.com
2


Part Number NB3M8T3910G
Description 2.5V/3.3V 3:1:10 Configurable Differential Clock Fanout Buffer
Maker ON Semiconductor
Total Page 20 Pages
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