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  ON Semiconductor Electronic Components Datasheet  

NB3N3002 Datasheet

HCSL Clock Generator

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NB3N3002
3.3V, Crystal to 25MHz,
100MHz, 125MHz and
200MHz HCSL Clock
Generator
Description
The NB3N3002 is a precision, low phase noise clock generator that
supports PCIExpress and Ethernet requirements. The device accepts
a 25 MHz fundamental mode parallel resonant crystal and generates a
differential HCSL output at 25 MHz, 100 MHz, 125 MHz or 200 MHz
clock frequencies. Outputs can interface with LVDS with proper
termination (See Figure 5).
This device is housed in 5.0 mm x 4.4 mm narrow body TSSOP 16
pin package.
Features
Uses 25 MHz Fundamental Mode Parallel Resonant Crystal
External Loop Filter is Not Required
HCSL Differential Output or LVDS with Proper Termination
For Selectable Multipliers of the Input Frequency
Output Enable with TriState Outputs
PCIe Gen1, Gen2, Gen3 Jitter Compliant
Typical TIE RMS jitter of 2.5 ps
Phase Noise: @ 100 MHz
Offset Noise Power
100 Hz 109.4 dBc
1 kHz 127.8 dBc
10 kHz 136.2 dBc
100 kHz 138.8 dBc
1 MHz 138.2 dBc
10 MHz 161.4 dBc
20 MHz 163.00 dBc
Operating Range 3.3 V ±5%
Industrial Temperature Range 40°C to +85°C
These are PbFree Devices
http://onsemi.com
16
1
TSSOP16
DT SUFFIX
CASE 948F
MARKING
DIAGRAM
16
NB3N
3002
ALYWG
1G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
(*Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
VDD
X1/CLK
25 MHz Clock or
Crystal X2
Clock Buffer
Crystal Oscillator
Phase
Detector
BM
Charge
Pump
VCO
HSCL
Output
CLK
CLK
GND
SEL0
Figure 1. NB3N3002 Simplified Logic Diagram
SEL1 OE IREF
© Semiconductor Components Industries, LLC, 2013
October, 2013 Rev. 6
1
Publication Order Number:
NB3N3002/D


  ON Semiconductor Electronic Components Datasheet  

NB3N3002 Datasheet

HCSL Clock Generator

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NB3N3002
SEL0
SEL1
GND
X1/CLK
X2
OE
GND
GND
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
Figure 2. Pin Configuration (Top View)
VDD
CLK
CLK
GND
VDD
NC
NC
IREF
Table 1. PIN DESCRIPTION
Pin Symbol
I/O
1 Sel0 Input
2 Sel1 Input
12, 16
4
5
6
3, 7, 8, 13
9
15
14
10,11
VDD
X1/CLK
X2
OE
GND
IREF
CLK
CLK
NC
Power Supply
Input
Input
Input
Power Supply
Output
HCSL or
LVDS Output
HCSL or
LVDS Output
Description
LVTTL/LVCMOS frequency select input 0. Internal pullup resistor to VDD. See output
select table 2 for details.
LVTTL/LVCMOS frequency select input 1. Internal pullup resistor to VDD. See output
select Table 2 for details.
Positive supply voltage pins are connected to +3.3 V supply voltage.
Crystal or Clock input. Connect to 25 MHz crystal source or singleended clock.
Crystal input. Connect to a 25 MHz crystal or leave unconnected for clock input.
Output enable tristates output when connected to GND. Internal pullup resistor to VDD.
Ground 0 V. These pins provide GND return path for the devices.
Output current reference pin. Precision resistor (typ. 475 W) is connected from pin 9 to
GND to set the output current.
Noninverted clock output. (For LVDS levels see Figure 5)
Inverted clock output. (For LVDS levels see Figure 5)
Do not connect
Table 2. OUTPUT FREQUENCY SELECT TABLE
WITH 25MHz CRYSTALS
SEL1*
L
SEL0*
L
CLK Multiplier
1x
fCLK (MHz)
25
LH
4x
100
HL
5x
125
HH
8x
200
*Pins SEL1 and SEL0 default high when left open.
Recommended Crystal Parameters
Crystal
Fundamental ATCut
Frequency
25 MHz
Load Capacitance
1620 pF
Shunt Capacitance, C0
7 pF Max
Equivalent Series Resistance 50 W Max
Initial Accuracy at 25 °C ±20 ppm
Temperature Stability
±30 ppm
Aging
±20 ppm
http://onsemi.com
2


Part Number NB3N3002
Description HCSL Clock Generator
Maker ON Semiconductor
Total Page 8 Pages
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