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NB3N106K
3.3V Differential 1:6 Fanout
Clock Driver with HCSL
Outputs
Description The NB3N106K is a differential 1:6 Clock fanout buffer with
High−speed Current Steering Logic (HCSL) outputs optimized for ultra low propagation delay variation. The NB3N106K is designed with HCSL PCI Express clock distribution and FBDIMM applications in mind.
Inputs can directly accept differential LVPECL, LVDS, and HCSL signals per Figures 7, 8, and 9. Single−ended LVPECL, HCSL, LVCMOS, or LVTTL levels are accepted with a proper external Vth reference supply per Figures 4 and 10. Input pins incorporate separate internal 50 W termination resistors allowing additional single ended system interconnect flexibility.
Output drive current is set by connecting a 475 W resistor from IREF (Pin 1) to GND per Figure 6.