NB3N1900K - 3.3V 100/133MHz Differential 1:19 HCSL Clock ZDB/Fanout Buffer

Datasheet Summary

Description

The NB3N1900K differential clock buffers are designed to work in conjunction with a PCIe compliant source clock synthesizer to provide point to

point clocks to multiple agents.

Features

Fixed Feedback Path for Lowest Input.
to.
Output Delay.
Eight Dedicated OE# Pins for Hardware Control of Outputs.
PLL Bypass Configurable for PLL or Fanout Operation.
Selectable PLL Bandwidth.
Spread Spectrum Compatible: Tracks Input Clock Spreading for Low EMI.
SMBus Programmable Configurations.
100 MHz and 133 MHz PLL Mode to Meet the Next Generation PCIe Gen2 / Gen 3 and Intel QPI Phase Jitter.
2 Tri.

ON Semiconductor

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Datasheet Details

Part number	NB3N1900K
Manufacturer	ON Semiconductor
File Size	229.27 KB
Description	3.3V 100/133MHz Differential 1:19 HCSL Clock ZDB/Fanout Buffer
Datasheet	NB3N1900K Datasheet
Additional preview pages of the NB3N1900K datasheet.

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Full PDF Text Transcription

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NB3N1900K 3.3V 100/133 MHz Differential 1:19 HCSL Clock ZDB/Fanout Buffer for PCIe[ Description The NB3N1900K differential clock buffers are designed to work in conjunction with a PCIe compliant source clock synthesizer to provide point−to−point clocks to multiple agents. The device is capable of distributing the reference clocks for Intel® QuickPath Interconnect (Intel QPI), PCIe Gen1, Gen2, Gen3. The NB3N1900K internal PLL is optimized to support 100 MHz and 133 MHz frequency operation. The NB3N1900K supports HCSL output levels.

Published: Jul 31, 2015 |