NB3N108K Overview
The NB3N108K is a differential 1:8 Clock fanout buffer with High−speed Current Steering Logic (HCSL) outputs optimized for ultra low propagation delay variation. The NB3N108K is designed with HCSL PCI Express clock distribution and FBDIMM applications in mind. Inputs can directly accept differential LVPECL, LVDS, HCSL signals per Figures 7, 8,.
NB3N108K Key Features
- Typical Input Clock Frequency 100, 133, 166, or 400 MHz
- 220 ps Typical Rise and Fall Times
- 800 ps Typical Propagation Delay
- Dtpd 100 ps Maximum Propagation Delay Variation Per Each Diff
- 0.1 ps Typical Integrated Phase Jitter RMS
- Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
- Differential HCSL Output Levels
- LVDS Output Levels with Interface Termination
- These are Pb-Free Devices