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NB3N108K - 3.3V Differential 1:8 Fanout Clock Data Driver

Datasheet Summary

Description

The NB3N108K is a differential 1:8 Clock fanout buffer with High

speed Current Steering Logic (HCSL) outputs optimized for ultra low propagation delay variation.

The NB3N108K is designed with HCSL PCI Express clock distribution and FBDIMM applications in mind.

Features

  • Typical Input Clock Frequency 100, 133, 166, or 400 MHz.
  • 220 ps Typical Rise and Fall Times.
  • 800 ps Typical Propagation Delay.
  • Dtpd 100 ps Maximum Propagation Delay Variation Per Each Diff Pair.
  • 0.1 ps Typical Integrated Phase Jitter RMS.
  • Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V.
  • Differential HCSL Output Levels.
  • LVDS Output Levels with Interface Termination.
  • These are Pb.
  • Free Devices.

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Datasheet preview – NB3N108K

Datasheet Details

Part number NB3N108K
Manufacturer ON Semiconductor
File Size 139.91 KB
Description 3.3V Differential 1:8 Fanout Clock Data Driver
Datasheet download datasheet NB3N108K Datasheet
Additional preview pages of the NB3N108K datasheet.

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Full PDF Text Transcription

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NB3N108K 3.3V Differential 1:8 Fanout Clock Data Driver with HCSL Outputs Description The NB3N108K is a differential 1:8 Clock fanout buffer with High−speed Current Steering Logic (HCSL) outputs optimized for ultra low propagation delay variation. The NB3N108K is designed with HCSL PCI Express clock distribution and FBDIMM applications in mind. Inputs can directly accept differential LVPECL, LVDS, HCSL signals per Figures 7, 8, and 9. Single−ended LVPECL, HCSL, LVCMOS, or LVTTL levels are accepted with a proper external Vth reference supply per Figures 4 and 10. Input pins incorporate separate internal 50 W termination resistors allowing additional single ended system interconnect flexibility.
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