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NB3N121K - 3.3V Differential 1:21 Fanout Clock and Data Driver

Datasheet Summary

Description

The NB3N121K is a differential 1:21 Clock and Data fanout buffer with High

speed Current Steering Logic (HCSL) outputs optimized for ultra low propagation delay variation.

The NB3N121K is designed with HCSL PCI Express clock distribution and FBDIMM applications in mind.

Features

  • Typical Input Clock Frequency 100, 133, 166, 200, 266, 333 and 400 MHz.
  • 340 ps Typical Rise and Fall Times.
  • 800 ps Typical Propagation Delay.
  • 100 ps Max Within Device Skew.
  • 150 ps Max Device.
  • to.
  • Device Skew.
  • Dtpd 100 ps Maximum Propagation Delay Variation Per Each Differential Pair.
  • 0.1 ps Typical RMS Additive Phase Jitter.
  • LVDS Output Levels Optional with Interface Termination.
  • Operating Range: VCC.

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Datasheet preview – NB3N121K

Datasheet Details

Part number NB3N121K
Manufacturer ON Semiconductor
File Size 131.12 KB
Description 3.3V Differential 1:21 Fanout Clock and Data Driver
Datasheet download datasheet NB3N121K Datasheet
Additional preview pages of the NB3N121K datasheet.

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Full PDF Text Transcription

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NB3N121K 3.3V Differential 1:21 Fanout Clock and Data Driver with HCSL Outputs Description The NB3N121K is a differential 1:21 Clock and Data fanout buffer with High−speed Current Steering Logic (HCSL) outputs optimized for ultra low propagation delay variation. The NB3N121K is designed with HCSL PCI Express clock distribution and FBDIMM applications in mind. Inputs can directly accept differential LVPECL, HCSL, and LVDS signals per Figures 7, 8, and 9. Single ended LVPECL, HCSL, LVCMOS, or LVTTL levels are accepted with a proper external Vth reference supply per Figures 4 and 10. Input pins incorporate separate internal 50 W termination resistors allowing additional single ended system interconnect flexibility.
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