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NB3N551 Datasheet

Ultra-Low Skew 1:4 Clock Fanout Buffer

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NB3N551
3.3 V / 5.0 V
Ultra-Low Skew
1:4 Clock Fanout Buffer
Description
The NB3N551 is a low skew 1to 4 clock fanout buffer, designed
for clock distribution in mind. The NB3N551 specifically guarantees
low outputtooutput skew. Optimal design, layout and processing
minimize skew within a device and from device to device.
The output enable (OE) pin threestates the outputs when low.
Features
Input/Output Clock Frequency up to 180 MHz
Low Skew Outputs (50 ps typical)
RMS Phase Jitter (12 kHz – 20 MHz): 43 fs (Typical)
Output goes to ThreeState Mode via OE
Operating Range: VDD = 3.0 V to 5.5 V
Ideal for Networking Clocks
Packaged in 8pin SOIC
Industrial Temperature Range
These are PbFree Devices
Q1
Q2
CLK
Q3
Q4
OE
Figure 1. Block Diagram
http://onsemi.com
8
1
SOIC8
D SUFFIX
CASE 751
MARKING
DIAGRAMS*
8
3N551
ALYW
G
1
3N551 = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
DFN8
MN SUFFIX
1
CASE 506AA
14
6K = Specific Device Code
M = Date Code
G = PbFree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
PIN CONNECTIONS
1
ICLK
Q1
2
3
Q2
Q3 4
8 OE
7
6
VDD
GND
5 Q4
ORDERING INFORMATION
Device
NB3N551DG
NB3N551DR2G
Package
SOIC8
(PbFree)
SOIC8
(PbFree)
Shipping
98 Units/Rail
2500/Tape & Reel
NB3N551MNR4G DFN8 1000/Tape & Reel
(PbFree)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2012
July, 2012 Rev. 4
1
Publication Order Number:
NB3N551/D


  ON Semiconductor Electronic Components Datasheet  

NB3N551 Datasheet

Ultra-Low Skew 1:4 Clock Fanout Buffer

No Preview Available !

NB3N551
Table 1. OE, OUTPUT ENABLE FUNCTION
OE Function
0 Disable
1 Enable
Table 2. PIN DESCRIPTION
Pin #
Name
Type
1 ICLK (LV)CMOS/(LV)TTL Input
2 Q1 (LV)CMOS/(LV)TTL Output
3 Q2 (LV)CMOS/(LV)TTL Output
4 Q3 (LV)CMOS/(LV)TTL Output
5 Q4 (LV)CMOS/(LV)TTL Output
6 GND
Power
7 VDD
Power
8 OE (LV)CMOS/(LV)TTL Input
EP Thermal Exposed Pad
Description
Clock Input. Internal pull-up resistor.
Clock Output 1
Clock Output 2
Clock Output 3
Clock Output 4
Negative supply voltage; Connect to ground, 0 V
Positive supply voltage (3.0 V to 5.5 V)
Output Enable for the clock outputs. Outputs are enabled when HIGH or when left
open; OE pin has internal pullup resistor. Threestates outputs when LOW.
(DFN8 only) Thermal exposed pad must be connected to a sufficient thermal
conduit. Electrically connect to the most negative supply (GND) or leave uncon-
nected, floating open.
http://onsemi.com
2


Part Number NB3N551
Description Ultra-Low Skew 1:4 Clock Fanout Buffer
Maker ON Semiconductor
Total Page 7 Pages
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