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NB3N51044 Datasheet Quad HCSL / LVDS Clock Generator

Manufacturer: onsemi

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Datasheet Details

Part number NB3N51044
Manufacturer onsemi
File Size 130.89 KB
Description Quad HCSL / LVDS Clock Generator
Datasheet download datasheet NB3N51044 Datasheet

Overview

NB3N51044 3.3 V, Crystal to 100 MHz / 125 MHz Quad HCSL / LVDS Clock Generator The NB3N51044 is a precision, low phase noise clock generator that supports PCI Express and sRIO clock requirements.

The device accepts a 25 MHz fundamental mode parallel resonant crystal or a 25 MHz single ended reference clock signal and generates four differential HCSL/LVDS outputs (See Figure 10 for LVDS interface) of 100 MHz or 125 MHz clock frequency based on frequency select input F_SEL.

NB3N51044 is configurable to bypass the PLL from signal path using BYPASS, and provides the output frequency through the divider network.

Key Features

  • Uses 25 MHz Fundamental Crystal or Reference Clock Input.
  • Four Low Skew HCSL or LVDS Outputs.
  • Output Frequency Selection of 100 MHz or 125 MHz.
  • Individual OE Tri.
  • States Outputs.
  • Master Reset and BYPASS Modes.
  • PCIe Gen 1, Gen 2, Gen 3 Compliant.
  • Typical Phase Jitter @ 125 MHz (Integrated 1.875 MHz to 20 MHz): 0.2 ps.
  • Typical Cycle.
  • Cycle Jitter @ 100 MHz (10k cycles): 20 ps.
  • Phase Noise @ 100 MHz: Off.

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