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NB3N501 - 3.3V / 5.0V 13 MHz to 160 MHz PLL Clock Multiplier

Datasheet Summary

Description

The NB3N501 is a clock multiplier that will generate one of nine selectable output multiples of an input frequency via two 3

level select inputs (S0, S1).

It accepts a standard fundamental mode crystal or an external reference clock signal.

Locked Loop (PLL) design tech

Features

  • Clock Output Frequencies up to 160 MHz.
  • Nine Selectable Multipliers of the Input Frequency.
  • Operating Range: VDD = 3.3 V ±10% or 5.0 V ±5%.
  • Low Jitter Output of 25 ps One Sigma (rms).
  • Zero ppm Clock Multiplication Error.
  • 45%.
  • 55% Output Duty Cycle.
  • TTL/CMOS Output with 25 mA TTL Le.

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Datasheet preview – NB3N501

Datasheet Details

Part number NB3N501
Manufacturer ON Semiconductor
File Size 102.32 KB
Description 3.3V / 5.0V 13 MHz to 160 MHz PLL Clock Multiplier
Datasheet download datasheet NB3N501 Datasheet
Additional preview pages of the NB3N501 datasheet.

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NB3N501 3.3V / 5.0V 13 MHz to 160 MHz PLL Clock Multiplier Description The NB3N501 is a clock multiplier that will generate one of nine selectable output multiples of an input frequency via two 3−level select inputs (S0, S1). It accepts a standard fundamental mode crystal or an external reference clock signal. Phase−Locked−Loop (PLL) design techniques are used to produce a low jitter, TTL level clock output up to 160 MHz with a 50% duty cycle. An Output Enable (OE) pin is provided, and when asserted low, the clock output goes into tri−state (high impedance).
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