NB3N51054 - Quad HCSL / LVDS Clock Generator

Product Overview

ON Semiconductor

Datasheet Details

Part number	NB3N51054
Manufacturer	ON Semiconductor
File Size	162.85 KB
Description	Quad HCSL / LVDS Clock Generator
Datasheet	NB3N51054 Datasheet
Additional preview pages of the NB3N51054 datasheet.

Product details

Description

Pin # Pin Name Type 1 CLK2 HCSL or LVDS output Description Noninverted clock output.(For LVDS levels see Figure 4) 2 CLK2 HCSL or LVDS Inverted clock output.(For LVDS levels see Figure 4) output 3 GND Ground Power supply ground 0 V.This pin provides GND return path for the device.4 VDD Power Positive supply voltage pin connected to +3.3 V typical supply voltage.5 CLK1 HCSL or LVDS Noninverted clock output.(For LVDS levels see Figure 4) output 6 CLK1 HCSL or LVDS Inv

Features

Uses 25 MHz Fundamental Crystal or Reference Clock Input.
Four Low Skew HCSL or LVDS Outputs.
I2C Support with Read Back Capability.
Spread of.
0.35%,.
0.5% and No Spread.
Individual Output Enable/Disable Control through I2C.
PCIe Gen 1, Gen 2, Gen 3 Compliant.
Typical Phase Jitter @ 100 MHz (Integrated 12 kHz to 20 MHz): 0.5 ps.
Typical Cycle.
Cycle Jitter @ 100 MHz (10k cycles): 20 ps.
Phas.

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Other Datasheets by ON Semiconductor

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Published: Jul 31, 2015 |