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NB3W1900L Datasheet

3.3V 100/133MHz Differential 1:19 HCSL-Compatible Push-Pull Clock ZDB/Fanout Buffer

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NB3W1900L
3.3 V 100/133 MHz
Differential 1:19
HCSL-Compatible Push‐Pull
Clock ZDB/Fanout Buffer for
PCIe[
www.onsemi.com
Description
The NB3W1900L differential clock buffers are designed to work in
conjunction with a PCIe compliant source clock synthesizer to provide
point-to-point clocks to multiple agents. The device is capable of
distributing the reference clocks for Intel® QuickPath Interconnect
(Intel QPI), PCIe Gen1/Gen2/Gen3.The NB3W1900L internal PLL is
optimized to support 100 MHz and 133 MHz frequency operation.
The NB3W1900L is developed with the low-power NMOS Push-Pull
buffer type.
Features
19 Low Power Differential Clock Output Pairs @ 0.7 V
Output-to-Output Skew Performance: < 85 ps
Cycle-to-Cycle Jitter (PLL Mode): < 50ps
Low Phase Jitter (Intel QPI, PCIe Gen 2/Gen 3 Phase Jitter
Compliant)
Input-to-Output Delay Variation: < 50 ps
Fixed-Feedback for Lowest Input-to-Output Delay Variation
Spread Spectrum Compatible; Tracks Input Clock Spreading for Low
EMI
100 MHz and 133 MHz PLL Mode to Meet the Next Generation
PCIe Gen2 / Gen 3 and Intel QPI Phase Jitter
Individual OE Control via SMBus
Low-Power NMOS Push-Pull HCSL−Compatible Outputs
PLL Configurable for PLL Mode or Bypass Mode
(Fanout Operation)
SMBus Address Configurable to Allow Multiple Buffers in a Single
Control Network
Programmable PLL Bandwidth
Two Tri-level Addresses Selection (Nine SMBus Addresses)
QFN 72-pin Package, 10 mm × 10 mm
These are Pb-Free Devices
1 72
QFN72
MN SUFFIX
CASE 485DK
MARKING DIAGRAM
1
NB3W
1900L
AWLYYWWG
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb-Free Package
ORDERING INFORMATION
See detailed ordering and shipping information on page 19 of
this data sheet.
© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 1
1
Publication Order Number:
NB3W1900L/D


  ON Semiconductor Electronic Components Datasheet  

NB3W1900L Datasheet

3.3V 100/133MHz Differential 1:19 HCSL-Compatible Push-Pull Clock ZDB/Fanout Buffer

No Preview Available !

NB3W1900L
CLK_IN
CLK_IN#
100M_133M#
HBW_BYP_LBW#
SA_0
SA_1
PWRGD/PWRDN#
SDA
SCL
SSC Compatible
PLL
MUX
Control
Logic
Figure 1. Simplified Block Diagram
FBOUT_NC
FBOUT_NC#
DIF[18:0]
DIF[18:0]#
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
VDDA
GNDA
100M_133M#
HBW_BYP_LBW#
PWRGD/PWRDN#
GND
VDDR
CLK_IN
CLK_IN#
SA_0
SDA
SCL
SA_1
FBOUT_NC#
FBOUT_NC
GND
DIF0
DIF0#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
NB3W1900L
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
54 DIF12#
53 DIF12
52 VDDIO
51 GND
50 DIF11#
49 DIF11
48 DIF10#
47 DIF10
46 GND
45 VDD
44 DIF9#
43 DIF9
42 DIF8#
41 DIF8
40 VDDIO
39 GND
38 DIF7#
37 DIF7
Figure 2. Pin Configuration
(Top View)
www.onsemi.com
2


Part Number NB3W1900L
Description 3.3V 100/133MHz Differential 1:19 HCSL-Compatible Push-Pull Clock ZDB/Fanout Buffer
Maker ON Semiconductor
Total Page 20 Pages
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