NB4L16M Datasheet | onsemi

2.5 V/3.3 V, 5 Gb/s Multi Level Clock/Data Input to CML Driver/Receiver/Buffer/ Translator with Internal Termination Description The NB4L16M is a differential driver/receiver/buffer/translator which can accept LVPECL, LVDS, CML, HSTL, LVCMOS/LVTTL and produce 400 m V CML output. The device is capable of receiving, buffering, and translating a clock or data signal that is as small as 75 m V operating up to 3.5 GHz or 5.0 Gb/s, respectively. As such, it is ideal for SONET, Gig E, Fiber Channel and backplane applications (see Table 6 and Figures 20, 21 22, and 23). Differential inputs incorporate internal 50 W termination resistors and accept LVPECL (Positive ECL), LVTTL/LVCMOS, CML, HSTL or LVDS. The differential 16 m A CML output provides matching internal 50 W termination, and 400 m V output swing when externally receiver terminated, 50 W to VCC (see Figure 19). These Features provide transmission line termination on chip, at the receiver and driver end, eliminating any use of additional external ponents. The VBB, an internally generated voltage supply, is available to this device only. For single-ended input configuration, the unused plementary differential input is connected to VBB as a switching reference voltage. The VBB reference output can be used also to re-bias capacitor coupled differential or single-ended output signals. For the capacitor coupled input signals, VBB should be connected to the VTD pin and bypassed to ground with a 0.01 m F capacitor. When not used VBB should be left open. This device is housed in a 3x3 mm 16 pin QFN package. Application notes, models, and support documentation are available at .onsemi.. Features - Maximum Input Clock Frequency up to 3.5 GHz - Maximum Input Data Rate up to 5.0 Gb/s - < 0.7 ps Maximum Clock RMS Jitter - < 10 ps Maximum Data Dependent Jitter at 2.5 Gb/s - 220 ps Typical Propagation Delay - 60 ps Typical Rise and Fall Times - CML Output with Operating Range: - VCC = 2.375 V to 3.6 V with VEE = 0...