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  ON Semiconductor Electronic Components Datasheet  

NB4L16M Datasheet

Multi Level Clock/Data Input to CML Driver / Receiver / Buffer / Translator

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NB4L16M pdf
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NB4L16M
2.5V/3.3V, 5 Gb/s Multi Level
Clock/Data Input to CML
Driver / Receiver / Buffer/
Translator with Internal
Termination
Description
The NB4L16M is a differential driver/receiver/buffer/translator
which can accept LVPECL, LVDS, CML, HSTL, LVCMOS/LVTTL
and produce 400 mV CML output. The device is capable of receiving,
buffering, and translating a clock or data signal that is as small as
75 mV operating up to 3.5 GHz or 5.0 Gb/s, respectively. As such, it is
ideal for SONET, GigE, Fiber Channel and backplane applications
(see Table 6 and Figures 20, 21 22, and 23).
Differential inputs incorporate internal 50 W termination resistors
and accept LVPECL (Positive ECL), LVTTL/LVCMOS, CML, HSTL
or LVDS. The differential 16 mA CML output provides matching
internal 50 W termination, and 400 mV output swing when externally
receiver terminated, 50 W to VCC (see Figure 19). These features
provide transmission line termination on chip, at the receiver and
driver end, eliminating any use of additional external components.
The VBB, an internally generated voltage supply, is available to this
device only. For singleended input configuration, the unused
complementary differential input is connected to VBB as a switching
reference voltage. The VBB reference output can be used also to
rebias capacitor coupled differential or singleended output signals.
For the capacitor coupled input signals, VBB should be connected to
the VTD pin and bypassed to ground with a 0.01 mF capacitor. When
not used VBB should be left open.
This device is housed in a 3x3 mm 16 pin QFN package.
Application notes, models, and support documentation are available at
www.onsemi.com.
Features
Maximum Input Clock Frequency up to 3.5 GHz
Maximum Input Data Rate up to 5.0 Gb/s
< 0.7 ps Maximum Clock RMS Jitter
< 10 ps Maximum Data Dependent Jitter at 2.5 Gb/s
220 ps Typical Propagation Delay
60 ps Typical Rise and Fall Times
CML Output with Operating Range:
VCC = 2.375 V to 3.6 V with VEE = 0 V
CML Output Level (400 mV PeaktoPeak Output),
Differential Output Only
50 W Internal Input and Output Termination Resistors
Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
EP, and SG Devices
PbFree Packages are Available
http://onsemi.com
1
QFN16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB4L
16M
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
VCC
VTD
50 W
D
D
50 W
VTD
R1
R2
R2
R1
Q
Q
VEE
Figure 1. Functional Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
February, 2006 Rev. 1
1
Publication Order Number:
NB4L16M/D


  ON Semiconductor Electronic Components Datasheet  

NB4L16M Datasheet

Multi Level Clock/Data Input to CML Driver / Receiver / Buffer / Translator

No Preview Available !

NB4L16M pdf
NB4L16M
VCC VBB VEE VEE
16 15 14 13
Exposed Pad (EP)
VTD 1
D2
D3
VTD 4
NB4L16M
12 VCC
11 Q
10 Q
9 VCC
5 678
VCC NC VEE VEE
Figure 2. Pin Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin Name
I/O
Description
1 VTD
Internal 50 W termination pin. See Table 4 (Note 1).
2
D
LVPECL, CML, HSTL,
Inverted differential input. Internal 36.5 kW to VCC and 73 kW to VEE
LVCMOS, LVDS, LVTTL Input (Note 1).
3
D
LVPECL, CML, HSTL,
Noninverted differential input. Internal 73 kW to VCC and 36.5 kW to VEE
LVCMOS, LVDS, LVTTL Input (Note 1).
4 VTD
15 VBB
6 NC
Internal 50 W termination pin. See Table 4. (Note 1)
Internally generated reference voltage supply.
No Connect pin. The No Connect (NC) pin is electrically connected to the
die and MUST be left open.
10 Q
CML Output
Noninverted differential output. Typically receiver terminated with 50 W
resistor to VCC.
11 Q
CML Output
Inverted differential output. Typically receiver terminated with 50 W resistor
to VCC.
7, 8, 13, 14
VEE
Negative supply voltage
5, 9, 12, 16
VCC
Positive supply voltage
EP
Exposed pad (EP). EP on the package bottom is thermally connected to the
die for improved heat transfer out of the package. The pad is not electrically
connected to the die, but is recommended to be soldered to VEE on the
PC Board.
1. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage and if no signal
is applied on D/D input then the device will be susceptible to selfoscillation.
http://onsemi.com
2


Part Number NB4L16M
Description Multi Level Clock/Data Input to CML Driver / Receiver / Buffer / Translator
Maker ON Semiconductor
Total Page 12 Pages
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