NB4L16M - 2.5V/3.3V, 5 Gb/s Multi Level Clock/Data Input to CML Driver/Receiver/Buffer/Translator

Product Overview

ON Semiconductor

Datasheet Details

Part number	NB4L16M
Manufacturer	ON Semiconductor
File Size	667.05 KB
Description	2.5V/3.3V, 5 Gb/s Multi Level Clock/Data Input to CML Driver/Receiver/Buffer/Translator
Datasheet	NB4L16M Datasheet
Additional preview pages of the NB4L16M datasheet.

Product details

Description

The NB4L16M is a differential driver/receiver/buffer/translator which can accept LVPECL, LVDS, CML, HSTL, LVCMOS/LVTTL and produce 400 mV CML output.The device is capable of receiving, buffering, and translating a clock or data signal that is as small as 75 mV operating up to 3.5 GHz or 5.0 Gb/s, respectively.As such, it is ideal for SONET, GigE, Fiber Channel and backplane applications (see Table 6 and Figures 20, 21 22, and 23).Differential inputs incorporate internal 50 W termination resis

Features

provide transmission line termination on chip, at the receiver and driver end, eliminating any use of additional external components. The VBB, an internally generated voltage supply, is available to this device only. For single-ended input configuration, the unused complementary differential input is connected to VBB as a switching reference voltage. The VBB reference output can be used also to re-bias capacitor coupled differential or single-ended output signals. For the capacitor coupled input.

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Published: Jan 12, 2007 |