900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf




  ON Semiconductor Electronic Components Datasheet  

NB4N855S Datasheet

Dual AnyLevelTM to LVDS Receiver/Driver/Buffer/ Translator

No Preview Available !

www.DataSheet4U.com
NB4N855S
3.3 V, 1.5 Gb/s Dual
AnyLevelto LVDS
Receiver/Driver/Buffer/
Translator
Description
NB4N855S is a clock or data Receiver/Driver/Buffer/Translator
capable of translating AnyLevelTM input signal (LVPECL, CML,
HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the
distance, noise immunity of the system design, and transmission line
media, this device will receive, drive or translate data or clock signals
up to 1.5 Gb/s or 1.0 GHz, respectively. This device is pin−for−pin
plug in compatible to the SY55855V in a 3.3 V applications.
The NB4N855S has a wide input common mode range of
GND + 50 mV to VCC − 50 mV. This feature is ideal for translating
differential or single−ended data or clock signals to 350 mV typical
LVDS output levels.
The device is offered in a small 10 lead MSOP package. NB4N855S
is targeted for data, wireless and telecom applications as well as high
speed logic interface where jitter and package size are main
requirements.
Application notes, models, and support documentation are available
at www.onsemi.com.
Features
Guaranteed Input Clock Frequency up to 1.0 GHz
Guaranteed Input Data Rate up to 1.5 Gb/s
490 ps Maximum Propagation Delay
1.0 ps Maximum RMS Jitter
180 ps Maximum Rise/Fall Times
Single Power Supply; VCC = 3.3 V ±10%
Temperature Compensated TIA/EIA−644 Compliant LVDS Outputs
GND + 50 mV to VCC − 50 mV VCMR Range
http://onsemi.com
1
Micro 10
M SUFFIX
CASE 846B
MARKING
DIAGRAM*
10
855S
AYW
1
A = Assembly Location
Y = Year
W = Work Week
*For additional marking information, refer to
Application Note AND8002/D.
D0 Q0
D0 Q0
D1 Q1
D1 Q1
Functional Block Diagram
Device DDJ = 7 ps
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
TIME (133 ps/div)
Figure 1. Typical Output Waveform at 1.5 Gb/s with K28.5
(VINPP = 100 mV, Input Signal DDJ = 24 ps)
© Semiconductor Components Industries, LLC, 2005
June, 2005 − Rev. 0
1
Publication Order Number:
NB4N855S/D


  ON Semiconductor Electronic Components Datasheet  

NB4N855S Datasheet

Dual AnyLevelTM to LVDS Receiver/Driver/Buffer/ Translator

No Preview Available !

NB4N855S
D0 1
D0 2
D1 3
D1 4
GND 5
10 VCC
9 Q0
8 Q0
7 Q1
6 Q1
Figure 2. Pin Configuration and Block Diagram
(Top View)
Table 1. PIN DESCRIPTION
Pin Name
I/O
Description
1 D0 LVPECL, CML, LVCMOS, Noninverted Differential Clock/Data D0 Input.
LVTTL, LVDS
2 D0 LVPECL, CML, LVCMOS, Inverted Differential Clock/Data D0 Input.
LVTTL, LVDS
3 D1 LVPEL, CML, LVDS LVCMOS, Noninverted Differential Clock/Data D1 Input.
LVTTL
4
D1
LVPECL, CML, LVDS
Inverted Differential Clock/Data D1 Input.
LVCMOS LVTTL
5 GND
− Ground. 0 V.
6 Q1
LVDS Output
Inverted Q1 output. Typically loaded with 100 W receiver termination
resistor across differential pair.
7 Q1
LVDS Output
Noninverted Q1 output. Typically loaded with 100 W receiver termination
resistor across differential pair.
8 Q0
LVDS Output
Inverted Q0 output. Typically loaded with 100 W receiver termination
resistor across differential pair.
9 Q0
LVDS Output
Noninverted Q0 output. Typically loaded with 100 W receiver termination
resistor across differential pair.
10 VCC
− Positive Supply Voltage.
http://onsemi.com
2


Part Number NB4N855S
Description Dual AnyLevelTM to LVDS Receiver/Driver/Buffer/ Translator
Maker ON Semiconductor
Total Page 10 Pages
PDF Download

NB4N855S Datasheet PDF

View PDF for Mobile








Similar Datasheet

1 NB4N855S Dual AnyLevelTM to LVDS Receiver/Driver/Buffer/ Translator
ON Semiconductor





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy