NB4N11M - Multi Level Clock/Data Input to CML Receiver/Buffer/Translator

Datasheet Summary

Description

The NB4N11M is a differential 1 to 2 clock/data distribution/translation chip with CML output structure, targeted for high

speed clock/data applications.

The device is functionally equivalent to the EP11, LVEP11, SG11 or 7L11M devices.

Features

Maximum Input Clock Frequency > 2.5 GHz.
Maximum Input Data Rate > 2.5 Gb/s.
Typically 1 ps of RMS Clock Jitter.
Typically 10 ps of Data Dependent Jitter @ 2.5 Gb/s, RL = 25 W.
420 ps Typical Propagation Delay.
150 ps Typical Rise and Fall Times.
Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V and VTT = 1.8 V to 3.6 V.
Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP, EP, and SG Devices.
These De.

ON Semiconductor

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Datasheet Details

Part number	NB4N11M
Manufacturer	ON Semiconductor
File Size	273.37 KB
Description	Multi Level Clock/Data Input to CML Receiver/Buffer/Translator
Datasheet	NB4N11M Datasheet
Additional preview pages of the NB4N11M datasheet.

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3.3 V, 2.5 Gb/s Multi Level Clock/Data Input to CML Receiver/Buffer/Translator NB4N11M Description The NB4N11M is a differential 1−to−2 clock/data distribution/translation chip with CML output structure, targeted for high−speed clock/data applications. The device is functionally equivalent to the EP11, LVEP11, SG11 or 7L11M devices. Device produces two identical differential output copies of clock or data signal operating up to 2.5 GHz or 2.5 Gb/s, respectively. As such, NB4N11M is ideal for SONET, GigE, Fiber Channel, Backplane and other clock/data distribution applications. Inputs accept LVPECL, CML, LVCMOS, LVTTL, or LVDS (See Table 5). The CML outputs are 16 mA open collector (See Figure 18) which requires resistor (RL) load path to VTT termination voltage.

Published: Jan 12, 2007 |