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NB4N11M - Multi Level Clock/Data Input to CML Receiver/Buffer/Translator

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ON Semiconductor

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NB4N11M Multi Level Clock/Data Input to CML Receiver/Buffer/Translator by ON Semiconductor - Datasheet Preview — Datasheet preview – NB4N11M

Datasheet Details

Part number	NB4N11M
Manufacturer	ON Semiconductor
File Size	273.37 KB
Description	Multi Level Clock/Data Input to CML Receiver/Buffer/Translator
Datasheet	NB4N11M Datasheet
Additional preview pages of the NB4N11M datasheet.

Product details

Description

The NB4N11M is a differential 1 to 2 clock/data distribution/translation chip with CML output structure, targeted for high speed clock/data applications.

Features

Maximum Input Clock Frequency > 2.5 GHz.
Maximum Input Data Rate > 2.5 Gb/s.
Typically 1 ps of RMS Clock Jitter.
Typically 10 ps of Data Dependent Jitter @ 2.5 Gb/s, RL = 25 W.
420 ps Typical Propagation Delay.
150 ps Typical Rise and Fall Times.
Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V and VTT = 1.8 V to 3.6 V.
Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP, EP, and SG Devices.
These De.

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Published: Jan 12, 2007 |