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NB4N11S - 3.3V 1:2 AnyLevel Input to LVDS Fanout Buffer /Translator

General Description

Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 EP Name Q0 Q0 Q1 Q1 VCC NC VEE VEE VTD D D VTD VCC VCC VCC VCC LVPECL, CML, LVDS, LVCMOS, LVTTL LVPECL, CML, LVDS, LVCMOS, LVTTL I/O LVDS Output LVDS Output LVDS Output LVDS Output Descri

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Datasheet Details

Part number NB4N11S
Manufacturer onsemi
File Size 131.38 KB
Description 3.3V 1:2 AnyLevel Input to LVDS Fanout Buffer /Translator
Datasheet download datasheet NB4N11S Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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NB4N11S 3.3 V 1:2 AnyLevel™ Input to LVDS Fanout Buffer / Translator The NB4N11S is a differential 1:2 Clock or Data Receiver and will accept AnyLevelTM input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to LVDS and two identical copies of Clock or Data will be distributed, operating up to 2.0 GHz or 2.5 Gb/s, respectively. As such, the NB4N11S is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock or Data distribution applications. The NB4N11S has a wide input common mode range from GND + 50 mV to VCC − 50 mV. Combined with the 50 W internal termination resistors at the inputs, the NB4N11S is ideal for translating a variety of differential or single−ended Clock or Data signals to 350 mV typical LVDS output levels.