NB4N11S Description
Typically loaded with 100 W receiver termination resistor across differential pair. Typically loaded with 100 W receiver termination resistor across differential pair. Typically loaded with 100 W receiver termination resistor across differential pair.
NB4N11S Key Features
- Maximum Input Clock Frequency > 2.0 GHz Maximum Input Data Rate > 2.5 Gb/s 1 ps Maximum of RMS Clock Jitter Typically 10
- For additional marking information, refer to Application Note AND8002/D
- Rev. 0
- LVPECL, CML, LVDS, LVCMOS, LVTTL LVPECL, CML, LVDS, LVCMOS, LVTTL
- I/O LVDS Output LVDS Output LVDS Output LVDS Output
- Description Non-inverted D output. Typically loaded with 100 W receiver termination resistor across differential pair. I