Description
2 system level description 2.1 overview 2.2 architecture 2.3 I/O control 2.4 format and frame rate 2.5 SCCB interface 2.6 power up sequence 2.7 standby and sleep 3 block level description 3.1 pixel array structure 4 image sensor core digital functions 4.1 mirror and flip 4.2 test pattern 4.3 AEC/AG
Features
-
support for output formats: RAW RGB and YUV support for image sizes: VGA, and QVGA, CIF and any size smaller support for black sun cancellation support for internal and external frame synchronization
standard SCCB serial interface digital video port (DVP) parallel output interface embedded one-time programmable (OTP) memory on-chip phase lock loop (PLL) embedded 1.5V regulator for core
00key specifications
active array size: 656 x 488 power supply: core: 1.5VDC +/- 5%.
OV7740 Datasheet
