PACE1753-SOS - CMOS/SOS SPACE PROCESSOR MICROPERIPHERAL
PYRAMID
Key Features
Implements the MIL-STD-1750A Instruction Set Architecture for Memory Management and Protection of up to 1 Megaword. All mapping memory (10,240 bits) for both the MMU and BPU functions are included on the chip. Designed to interface memory to the PACE1750A/AE. Provides the following additional functions:.
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PACE1753/SOS SINGLE CHIP, MIL-STD-1750A MEMORY MANAGEMENT UNIT (MMU) CMOS/SOS SPACE PROCESSOR MICROPERIPHERAL FEATURES Implements the MIL-STD-1750A Instruction Set Archit...
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ERIPHERAL FEATURES Implements the MIL-STD-1750A Instruction Set Architecture for Memory Management and Protection of up to 1 Megaword. All mapping memory (10,240 bits) for both the MMU and BPU functions are included on the chip. Designed to interface memory to the PACE1750A/AE. Provides the following additional functions: — EDAC, Error Detection and Correction—or parity generation and detection — Correct data register—for diagnostics — First memory failing address register — Illegal address error detection— programmable — Multi-Master arbitration 8-bit extended address laches and drivers on chip.
PACE1753-SOS Datasheet
