PLL52C63-01 Datasheet PDF (Pentium/SDRAM Clock Generator)

PLL52C63-01 - Pentium/SDRAM Clock Generator

Description

NAME VDD VDDq2 VSS XIN XOUT BCLK_F/F1 BCLK_0/F2 48MHZ/F0 BCLK_F, BCLK(0:5) PCLK(0:3) SDRAM(0:11) SDATA SCLK BCLK5//PCISTP REF1//CPUSTP 48MHZ/F0 24MHZ/MODE REF(0:1) IOAPIC PIN NUM BER 1,6,14, 19,30,36 42,48 3,9,16,22 27,33,39,45 4 5 7,8,26 7,8,10,11 12,13,15 44,43,41,40 38,3

Features

n Generates all clock frequencies for Pentium (II), AMD and Cyrix system requiring multiple CPU clocks. n Supports up to16 Synchronous CPU clocks (4 CPU and 12 SDRAM) and 7 Synchronous PCI BUS clocks. n Two 14.318Mhz reference clocks and one 2.5V IOAPIC n One 24Mhz floppy clock and one 48Mhz USB clock. n Power management control pins to stop CPU, SDRAM or PCI BUS clocks. n Supports 2-wire I2C serial bus interface. n 50% duty cycle with low jitter n Mixed voltage support from 3.0 to 5V or (VDDq2=.

Datasheet Details

Part number	PLL52C63-01
Manufacturer	PhaseLink
File Size	198.32 KB
Description	Pentium/SDRAM Clock Generator
Datasheet	PLL52C63-01 Datasheet
Additional preview pages of the PLL52C63-01 datasheet.

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Full PDF Text Transcription

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PLL52C63-01 Pen tium/SDRAM Clock Gen er ator with In te grated Buff ers FEATURES n Generates all clock frequencies for Pentium (II), AMD and Cyrix system requiring multiple CPU clocks. n Supports up to16 Synchronous CPU clocks (4 CPU and 12 SDRAM) and 7 Synchronous PCI BUS clocks. n Two 14.318Mhz reference clocks and one 2.5V IOAPIC n One 24Mhz floppy clock and one 48Mhz USB clock. n Power management control pins to stop CPU, SDRAM or PCI BUS clocks. n Supports 2-wire I2C serial bus interface. n 50% duty cycle with low jitter n Mixed voltage support from 3.0 to 5V or (VDDq2=2.5V) n Available in 300mil 48 pin SSOP. PIN INFORMATION FREQUENCY SELECTION (MHz) F2 0 0 0 0 1 1 1 1 F1 0 0 1 1 0 0 1 1 F0 PCLK/SDRAM 0 1 0 1 0 1 0 1 50 100 83.3 68.5 55 75 60 66.6 BCLK 25 50 41.6 34.2 27.5 37.

Published: Sep 29, 2014 |