PhaseLink Datasheet | Specifications & PDF Download

PLL52C61-01HA/-21HA Pentium/SDRAM Clock Generator with Integrated Buffers FEATURES n Generates all clock frequencies for Pentium, AMD and Cyrix syste

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m PLL620-05/-06/-07/-08/-09 o c . XO with multipliers (for 120-200MHz Fund Xtal) Low Phase Noise U Universal Low Phase Noise IC’s 4 t e e FEATURES h P

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PLL102-03 Low Skew Output Buffer FEATURES Frequency range 75 ~ 180MHz. Internal phase locked loop will allow spread spectrum modulation on reference c

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FEATURES • • w w• • • • • • • • w Generates all clock frequencies for VIA K7 chip sets requiring multiple CPU clocks and high speed SDRAM buffers.

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m Preliminary PLL602-35/-37/-38/-39 o c . 750kHz – 800MHz Low Phase Noise Multiplier XO U Universal Low Phase Noise IC’s 4 t e FEATURES e PIN CONFIGUR

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m PLL620-05/-06/-07/-08/-09 o c . XO with multipliers (for 120-200MHz Fund Xtal) Low Phase Noise U Universal Low Phase Noise IC’s 4 t e e FEATURES h P

Rating: 1 ★ (3 votes)

m PLL620-05/-06/-07/-08/-09 o c . XO with multipliers (for 120-200MHz Fund Xtal) Low Phase Noise U Universal Low Phase Noise IC’s 4 t e e FEATURES h P

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m o .c U 4 t e FEATURES e h • Full swing CMOS S outputs with 25 mA drive capability a at TTL levels. t 10-27MHz fundamental crystal or • Reference a c

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FEATURES • • • w • • • • • • • w w Full swing CMOS outputs with 25 mA drive capability at TTL levels. Reference 10-27MHz crystal or clock. Integr

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m o .c U 4 t e FEATURES e h • Full swing CMOS S outputs with 25 mA drive capability a at TTL levels. t 20-30MHz crystal or clock. • Reference a • Inte

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96MHz – 400MHz Low Phase Noise XO (for 12 – 25MHz Crystals) FEATURES • • • • • • w 62 mil w w Low phase noise output for the 96MHz to 400MHz rang

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PL611-05 Programmable Quick Turn Clock T M FEATURES Advanced programmable PLL design Very low Jitter and Phase Noise (30-70ps Pk-Pk typical) Up to 2 p

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(Preliminary) PL611s-17 1.8V-3.3V PicoPLL TM KHz to MHz Programmable Clock FEATURES • Advanced Programmable PLL design for lowfrequency (kHz) input

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(Preliminary) PL611s-18 0.5kHz-125MHz MHz to KHz Programmable Clock T M FEATURES • Designed for Very Low-Power applications • Offered in Tiny GREEN/

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P521-23 Low Phase Noise PECL VCXO (100MHz to 200MHz) PAD ASSIGNMENT AND DESCRIPTION Pin # 1 2 3 www.DataSheet4U.com4 Name OSCOFFSEL GNDOSC VCON XIN X

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PLL102-04 Low Skew Output Buffer FEATURES Frequency range 50 ~ 120MHz. Internal phase locked loop will allow spread spectrum modulation on reference c

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Preliminary PLL102-109 Programmable DDR Zero Delay Clock Driver FEATURES PLL clock distribution optimized for Double Data Rate SDRAM application up

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PLL102-15 Low Skew Output Buffer FEATURES Frequency range 25 ~ 60MHz. Internal phase locked loop will allow spread spec trum modulation on reference c

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PLL520-00 www.DataSheet4U.com Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal) DIE CONFIGURATION 65 mil FEATURES • • 100MHz to 200MH

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PLL520-05/-06/-07/-08/-09 www.DataSheet4U.com Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal) PIN CONFIGURATION (Top View) VDD XIN X

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