Description
m PLL620-05/-06/-07/-08/-09 o c .XO with multipliers (for 120-200MHz Fund Xtal) Low Phase Noise U Universal Low Phase Noise IC’s 4 t e e .
GND
GND
GND
BLOCK DIAGRAM
SEL
^: Internal pull-up.
: PLL620-06 pin 12 is output drive select (DRIVSEL) (0 for High Drive CMOS, 1 for Standar.
Features
* h PIN CONFIGURATION S (Top View) a200MHz Fundamental Mode Crystal.
* 120MHz to t
* Output a range: 120
* 200MHz (no multiplication), D 240
* 400MHz (2x multiplier) or 480
* 700MHz . (4x multiplier). w
* w High yield design support up to 2pF string at 20
