PLL620-09 Datasheet, Xo, PhaseLink

✔ PLL620-09 Features

h PIN CONFIGURATION S (Top View) a200MHz Fundamental Mode Crystal.
120MHz to t
Output a range: 120
200MHz (no multiplication), D 240
400MHz (2x multiplier) or 480

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PLL620-09

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PhaseLink

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📄 Datasheet

Description:

(pll620-05/06/07/08/09) low phase noise xo. GND GND GND BLOCK DIAGRAM SEL ^: Internal pull-up *: PLL620-06 pin 12 is output drive select (DRIVSEL) (0 for High Drive CMOS,

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PLL620-09 PLL620-05 Low Phase Noise PhaseLink