PLL620-09, PLL620-05 Datasheet - PhaseLink

PLL620-09 - (PLL620-05/06/07/08/09) Low Phase Noise XO

GND GND GND BLOCK DIAGRAM SEL ^: Internal pull-up *: PLL620-06 pin 12 is output drive select (DRIVSEL) (0 for High Drive CMOS, 1 for Standard Drive CMOS) OE Q Q X+ X- Oscillator Amplifier PLL (Phase Locked Loop) OUTPUT ENABLE LOGICAL LEVELS Part # PLL620-08 PLL620-05 PLL620-06 PLL620-.

PLL620-09 Features

* h PIN CONFIGURATION S (Top View) a200MHz Fundamental Mode Crystal.

* 120MHz to t

* Output a range: 120

* 200MHz (no multiplication), D 240

* 400MHz (2x multiplier) or 480

* 700MHz . (4x multiplier). w

* w High yield design support up to 2pF string at 20

PLL620-05_PhaseLink.pdf