PLL601-15 - Low Phase Noise PLL Clock Multiplier

Product Overview

PhaseLink

Part number	PLL601-15
Manufacturer	PhaseLink
File Size	102.81 KB
Description	Low Phase Noise PLL Clock Multiplier
Datasheet	PLL601-15 Datasheet
Additional preview pages of the PLL601-15 datasheet.

The PLL601-15 is a low cost, high performance and low phase noise clock synthesizer.

It implements PhaseLink’s proprietary analog and digital Phase Locked Loop techniques for a fixed 5x multiplier.

e h.
Full swing CMOS S outputs with 25 mA drive capability a at TTL levels. t 20-30MHz crystal or clock.
Reference a.
Integrated crystal load capacitor: no external . D load capacitor required. w.
Output clocks up to 150MHz at 3.3V. w.
Low phase noise (-126dBc/Hz @ 1kHz). w.
Output Enable function.
Preliminary PLL601-15 Low Phase Noise PLL Clock Multiplier PIN.

PLL0210A - PHASE LOCKED LOOP (Z-Communications)
PLL0930A - PHASE LOCKED LOOP (Z-Communications)
PLL1000A - PHASE LOCKED LOOP (Z-Communications)
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PLL102-04 - Low Skew Output Buffer (PhaseLink Corporation)
PLL102-05 - Low Skew Output Buffer (PhaseLink Corporation)
PLL102-10 - Low Skew Output Buffer (PhaseLink Corporation)
PLL102-108 - Programmable DDR Zero Delay Clock Driver (PhaseLink Corporation)
PLL102-109 - Programmable DDR Zero Delay Clock Driver (PhaseLink Corporation)
PLL102-15 - Low Skew Output Buffer (PhaseLink Corporation)

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Published: Feb 10, 2006 |