74F821 Datasheet | Philips Semiconductors

DESCRIPTION The 74F821 series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of busses carrying parity. The 74F821/74F822 are buffered 10-bit wide versions of the popular 74F374/74F534 functions. The 74F822 is the inverted output version of 74F821. The 74F823 and 74F824 are 9-bit wide buffered registers with clock enable (CE) and master reset (MR) which are ideal for parity bus interfacing in high microprogrammed systems. The 74F824 is the inverted version of 74F823. The 74F825 and 74F826 are 8-bit buffered registers with all the 74F823/74F824 controls plus output enable (OE0, OE1, OE2) to allow multiuser control of the interface, e.g., CS, DMA, and RD/WR. They are ideal for uses as an output port requiring high IOL/IOH. The 74F826 is the inverted version of 74F825. TYPICAL fmax 180MHz 180MHz 180MHz TYPICAL SUPPLY CURRENT (TOTAL) 75m A 70m A 65m A FEATURES flip-flops - High speed parallel registers with positive edge-triggered D-type - High performance bus interface buffering for wide data/address paths or busses carrying parity - High impedance PNP base inputs for reduced loading (20µA in high and low states) - IIL is 20µA vs 1000µA for AM29821 series - Buffered control inputs to reduce AC effects - Ideal where high speed, light loading, or increased fan-in as required with MOS microprocessor - Positive and negative over-shoots are clamped to ground - 3-State outputs glitch free during power-up and power-down - Slim Dip 300 mil package - Broadside pinout patible with AMD AM 29821-29826 series - Outputs sink 64m A and source 24m A - Industrial temperature range available (- 40°C to +85°C) for 74F823 TYPE 74F821, 74F822 74F823, 74F824 74F825, 74F826 ORDERING INFORMATION ORDER CODE DESCRIPTION MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F821N, N74F822N, N74F823N, N74F824N, N74F825N, N74F826N N74F821D, N74F822D, N74F823D, N74F824D, N74F825D,...