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74F821 - Bus interface registers

Description

The 74F821 series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of busses carrying parity.

Features

  • flip-flops.
  • High speed parallel registers with positive edge-triggered D-type.
  • High performance bus interface buffering for wide data/address paths or busses carrying parity.
  • High impedance PNP base inputs for reduced loading (20µA in high and low states).
  • IIL is 20µA vs 1000µA for AM29821 series.
  • Buffered control inputs to reduce AC effects.
  • Ideal where high speed, light loading, or increased fan-in as required with MOS microprocessor.

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Full PDF Text Transcription

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INTEGRATED CIRCUITS 74F821/822/823/824/825/826 Bus interface registers Product specification IC15 Data Handbook 1996 Jan 05 Philips Semiconductors Philips Semiconductors Product specification Bus interface registers 74F821/822/823/824/825/826 74F821 74F822 74F823 74F824 74F825 74F826 10-bit bus interface register, non-inverting (3-State) 10-bit bus interface register, inverting (3-State) 9-bit bus interface register, non-inverting (3-State) 9-bit bus interface register, inverting (3-State) 8-bit bus interface register, non-inverting (3-State) 8-bit bus interface register, inverting (3-State) DESCRIPTION The 74F821 series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address path
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