74HC133 Datasheet | Philips Semiconductors

FEATURES - Output capability: standard - ICC category: SSI GENERAL DESCRIPTION The HC133 is an high-speed Si-gate CMOS device and is pin patible with low power Schottky TTL (LSTTL). It is specified in pliance with JEDEC standard no. 7A. The 74HC133 provides the 13-input NAND function. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns SYMBOL t PHL/t PLH CI CPD PARAMETER propagation delay A..M to Y input capacitance power dissipation per gate notes 1 and 2 CONDITIONS CL = 15 p F; VCC = 5 V 9 3.5 19 TYPICAL ns p F p F UNIT Notes to the quick reference data 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in p F; fo = output frequency in MHz; VCC = supply voltage in V; ∑ (CL × VCC2 × fo) = sum of the outputs. 2. For HC the condition is VI = GND to VCC ORDERING INFORMATION PACKAGES TYPE NUMBER PINS 74HC133N 74HC133D 16 16 DIL SO PIN POSITION MATERIAL plastic plastic SOT38 SOT109A CODE See also “74HC/HCT/HCU/HCMOS Logic Package Information”. September 1993 Philips Semiconductors Product specification 13-input NAND gate PINNING PIN NO. 1..7, 10.. 15 8 9 16 GND Y VCC SYMBOL A.. G, H..M data input ground (0 V) data output positive supply voltage NAME AND FUNCTION Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. September 1993 Philips Semiconductors Product specification 13-input NAND gate Fig.4 Functional diagram; Y = ABCDEFGHIJKLM. Fig.5 Logic diagram. FUNCTION TABLE INPUTS A L X X X X X X X X X X X X H Notes 1. H = HIGH voltage level L = LOW voltage level X = don’t care B X L X X X X X X X X X X X H C X X L X X X X X X X X X X H D X X X L X X X X X X X X X H E X X X X L X X X X X X X X H F X X X X X L X X X X X X X H G X X X X X X L X X X X X X H H X X X X X X X L X X X X X H I X X X X X X X X L X X X X H J X X X X X X X X X L X X X H K X X X X X X X X X X L X X H L X X X X...