13-input NAND gate
• Output capability: standard
• ICC category: SSI
The HC133 is an high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL).
It is specified in compliance with JEDEC standard no. 7A.
The 74HC133 provides the 13-input NAND function.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
propagation delay A..M to Y
power dissipation per gate
CL = 15 pF; VCC = 5 V
notes 1 and 2
Notes to the quick reference data
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
∑ (CL × VCC2 × fo) = sum of the outputs.
2. For HC the condition is VI = GND to VCC
See also “74HC/HCT/HCU/HCMOS Logic Package Information”.