QL3060 - PLD Gate pASIC 3 FPGA Combining High Performance and High Density

QuickLogic Corporation

Key Features

1000 1.0800 1.0600 1.0400 Kv 1.0200 1.0000 0.9800 www. DataSheet4U. com 0.9600 0.9400 0.9200 3 3.1 3.2 3.3 3.4 3.5 3.6 Supply Voltage (V) Figure 3: Voltage Factor vs. Supply Voltage Temperature Factor vs. Operating Temperature 1.15 1.10 1.05 1.00 0.95 0.90 0.85 -60 -40 -20 0 20 40 60 80 Kt Junction Temperature C Figure 4: Temperature Factor vs. Op.

QL3060 pld gate pasic 3 fpga combining high performance and high density by QuickLogic Corporation - Datasheet Preview

Datasheet Details

Part number	QL3060
Manufacturer	QuickLogic Corporation
File Size	564.31 KB
Description	PLD Gate pASIC 3 FPGA Combining High Performance and High Density
Datasheet	QL3060 Datasheet

Full PDF Text Transcription for QL3060 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for QL3060. For precise diagrams, and layout, please refer to the original PDF.

QL3060 pASIC 3 FPGA Data Sheet •••••• 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density • ...

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and High Density Device Highlights High Performance & High Density • 60,000 Usable PLD Gates with 316 I/Os • 300 MHz 16-bit www.DataSheet4U.com Eight Low-Skew Distributed Networks • Two array clock/control networks available Counters, 400 MHz Datapaths • 0.

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