QL3004E Datasheet | QuickLogic Corporation

4/( S$6,& )3- $ 'DWD 6KHHW ‡‡‡‡‡‡ 8VDEOH 3/' - DWH S$6,& )3- $ &RPELQLQJ +LJK 3HUIRUPDQFH DQG +LJK 'HQVLW 'HYLFH +LJKOLJKWV +LJK 3HUIRUPDQFH .. ‡ 300 MHz 16-bit +LJK 'HQVLW )RXU /RZ6NHZ 'LVWULEXWHG 1HWZRUNV ‡ Two array clock/control networks available ‡ 4,000 Usable PLD Gates with 82 I/Os Counters, 400 MHz Datapaths ‡ 0.35 µm four-layer metal non-volatile CMOS process for smallest die sizes (DVWR8VH )DVW 'HYHORSPHQW &FOHV ‡ 100% routable with 100% utilization and to the logic cell flip-flop clock, set and reset inputs - each driven by an input-only pin ‡ Two global clock/control networks available to the logic cell; F1, clock, set and reset inputs and the data input, I/O register clock, reset and enable inputs as well as the output enable control - each driven by an inputonly or I/O pin, or any logic cell output or I/O cell feedback plete pin-out stability ‡ Variable-grain logic cells provide high performance and 100% utilization ‡ prehensive design tools include high quality Verilog/VHDL synthesis +LJK 3HUIRUPDQFH ‡ Input + logic cell + output total delays under 6 ns ‡ Data path speeds over 400 MHz ‡ Counter speeds over 300 MHz $GYDQFHG ,2 &DSDELOLWLHV ‡ Interfaces with both 3.3 V and 5.0 V devices ‡ PCI pliant with 3.3 V and 5.0 V buses for -1/-2/-3/-4 speed grades ‡ Full JTAG boundary scan ‡ I/O Cells with individually controlled Registered Input Path and Output Enables 7RWDO RI ,2 3LQV ‡ 74 bidirectional input/output pins, PCI-pliant for 5.0 V and 3.3 V buses for -1/-2/-3/-4 speed grades ‡ Four High-Drive input-only pins ‡ Four High-Drive/distributed network pins )LJXUH S$6,& /RJLF &HOOV ‹ 4XLFN/RJLF &RUSRUDWLRQ Preliminary ZZZTXLFNORJLFFRP ‡ ‡ ‡ ‡ ‡ ‡ 4/( S$6,& )3- $ 'DWD 6KHHW 5HY...