QL3004E Datasheet PDF

4/ ( S$6,& )3*$ 'DWD 6KHHW ‡‡‡‡‡‡ 8VDEOH 3/' *DWH S$6,& )3*$ &RPELQLQJ +LJK 3HUIRUPDQFH DQG +LJK 'HQVLW\ 'HYLFH +LJKOLJKWV +LJK 3HUIRUPDQFH ‡ 300 MHz 16-bit +LJK 'HQVLW\ )RXU /RZ 6NHZ 'LVWULEXWHG 1HWZRUNV ‡ Two array clock/control networks available ‡ 4,000 Usable PLD Gates with 82 I/Os Counters, 400 MHz Datapaths ‡ 0.35 µm four-layer metal non-volatile CMOS process for smallest die sizes (DV\ WR 8VH )DVW 'HYHORSPHQW &\FOHV ‡ 100% routable with 100% utilization and to the logic cell flip-flop clock, set and reset inputs — each driven by an input-only pin ‡ Two global clock/control networks available to the logic cell; F1, clock, set and reset inputs and the data input, I/O register clock, reset and enable inputs as well as the output enable control — each driven by an inputonly or I/O pin, or any logic cell output or I/O cell feedback complete pin-out stability ‡ Variable-grain logic cells provide high performance and 100% utilization ‡ Comprehensive design tools include high quality V...