QL3060 Overview
QL3060 pASIC 3 FPGA Data Sheet 60,000 Usable PLD Gate pASIC 3 FPGA bining High Performance and High Density Device Highlights High Performance & High Density 60,000 Usable PLD Gates with 316 I/Os 300 MHz 16-bit .. 1,584 pASIC 3 Logic Cells © 2002 QuickLogic Corporation .quicklogic. 1 QL3060 pASIC 3 FPGA Data Sheet Rev D Architecture Overview The QL3060 is a 60,000 usable PLD gate member of the pASIC 3 family of...