QL3025 Overview
QL3025 pASIC 3 FPGA Data Sheet 25,000 Usable PLD Gate pASIC 3 FPGA bining High Performance and High Density Device Highlights High Performance & High Density 25,000 Usable PLD Gates with 204 I/Os 300 MHz 16-bit .. Four Low-Skew Distributed Networks Two array clock/control networks available Counters, 400 MHz Datapaths 0.35 µm four-layer metal non-volatile CMOS process for smallest die sizes Easy to Use / Fast...