557G06LF Datasheet - Renesas

2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX

* Packaged in 20-pin TSSOP

* Pb (lead) free packaging

* Operating voltage of 3.3 V

* Low power consumption

* Input differential clock of up to 200 MHz

* Jitter 60 ps (cycle-to-cycle)

* Output-to-output skew of 50 ps

* Available in indus

557G06LF

287.74 KB

2 to 4 differential pcie gen1 clock mux.

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557G06LF DIFFERENTIAL PCIE GEN1 CLOCK MUX Renesas

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