* ▪ 2, 4, 6, or 8 100MHz PCIe output pairs ▪ One 3.3V LVCMOS REF output with Wake-On- LAN (WOL) support ▪ See AN-891 for easy AC-coupling to other logic families Key Specifications ▪ 40fs RMS typical jitter (PCIe Gen6 CC) ▪ < 50ps cycle-to-cycle jitter on differential outputs ▪ < 50ps output-to-output
9FGL0851D
1.39 MB
3.3v pcie gen1-6 clock generator.
9FGL02x1/04x1/06x1/08x1D 3.3V PCIe Gen1-6 Clock Generator Family Datasheet The 9FGL02x1/04x1/06x1/08x1D devices comprise a family of 3.3V PCIe Gen1<.
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