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HD74CDC2509B - 3.3-V Phase-lock Loop Clock Driver

Description

The HD74CDC2509B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver.

It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

It is specifically designed for use with synchronous DRAMs.

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Datasheet preview – HD74CDC2509B

Datasheet Details

Part number HD74CDC2509B
Manufacturer Renesas
File Size 214.56 KB
Description 3.3-V Phase-lock Loop Clock Driver
Datasheet download datasheet HD74CDC2509B Datasheet
Additional preview pages of the HD74CDC2509B datasheet.

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Full PDF Text Transcription

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HD74CDC2509B 3.3-V Phase-lock Loop Clock Driver REJ03D0825-0900 (Previous: ADE-205-218G) Rev.9.00 Apr 07, 2006 Description The HD74CDC2509B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The HD74CDC2509B operates at 3.3 V VCC and is designed to drive up to five clock loads per output. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of the input clock. Output signal duty cycles are adjusted to 50 percent independent of the duty cycle at the input clock.
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