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HD74CDCF2509B Datasheet

3.3-V Phase-lock Loop Clock Driver

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HD74CDCF2509B
140 MHz, 0 to 85°C Operation
3.3-V Phase-lock Loop Clock Driver
REJ03D0827-1000
(Previous: ADE-205-224H)
Rev.10.00
Apr 07, 2006
Description
The HD74CDCF2509B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a phase-lock
loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input
signal. It is specifically designed for use with synchronous DRAMs. The HD74CDCF2509B operates at 3.3 V VCC and
is designed to drive up to five clock loads per output.
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of the input clock.
Output signal duty cycles are adjusted to 50 percent independent of the duty cycle at the input clock. Each bank of
outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the
outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low
state.
Unlike many products containing PLLs, the HD74CDCF2509B does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, HD74CDCF2509B requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required, following power up and application of a
fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals.
Features
Supports PC133 and meets “PC SDRAM registered DIMM specification, Rev. 1.1”
Phase-lock loop clock distribution for synchronous DRAM applications
External feedback (FBIN) pin is used to synchronize the outputs to the clock input
No external RC network required
Support spread spectrum clock (SSC) synthesizers
Supports frequencies up to 140 MHz
0 to 85°C operating range
Ordering Information
Part Name
Package Type
HD74CDCF2509BTEL TSSOP-24 pin
Package Code
(Previous code)
PTSP0024JB-A
(TTP-24DBV)
Package
Abbreviation
T
Taping Abbreviation
(Quantity)
EL (1,000 pcs / Reel)
Rev.10.00 Apr 07, 2006 page 1 of 8


Renesas Electronics Components Datasheet

HD74CDCF2509B Datasheet

3.3-V Phase-lock Loop Clock Driver

No Preview Available !

HD74CDCF2509B
Function Table
1G
X
L
L
H
H
H : High level
L : Low level
X : Immaterial
Inputs
2G
X
L
H
L
H
Pin Arrangement
CLK
L
H
H
H
H
1Y (0:4)
L
L
L
H
H
Outputs
2Y (0:3)
L
L
H
L
H
AGND 1
VCC 2
1Y0 3
1Y1 4
1Y2 5
GND 6
GND 7
1Y3 8
1Y4 9
VCC 10
1G 11
FBOUT 12
(Top view)
24 CLK
23 AVCC
22 VCC
21 2Y0
20 2Y1
19 GND
18 GND
17 2Y2
16 2Y3
15 VCC
14 2G
13 FBIN
FBOUT
L
H
H
H
H
Rev.10.00 Apr 07, 2006 page 2 of 8


Part Number HD74CDCF2509B
Description 3.3-V Phase-lock Loop Clock Driver
Maker Renesas
Total Page 9 Pages
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