dual j-k flip-flops.
* High Speed Operation: tpd (Clock to Q) = 21 ns typ (CL = 50 pF)
* High Output Current: Fanout of 10 LSTTL Loads
* Wide Operating Voltage: VCC = 2 to 6 V
Each flip-flop has independent J, K, preset, clear, and clock inputs and Q and Q outputs. This device is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Clear and preset are independent of the c.
Image gallery
TAGS
Download (Size : 200.82KB)