8-bit Shift Register
May 10, 2006
The inputs are buffered to lower the drive requirements to one series 74 or 74LS standard load, respectively. Input
clamping diodes minimize switching transients and simplify system design. This parallel in or serial-in, serial-out shift
register has a complexity of 77 equivalent gates on a monolithic chip. This device features gated clock inputs and an
overriding clear input.
The parallel-in or serial-in modes are established by the shift / load input.
When high, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock
pulse. When low, the parallel (broadside) data inputs are enabled and synchronous loading occurs on the next clock
pulse, during parallel loading, serial data flow is inhibited.
This, of course, allows the system clock to be free running and the register can be stopped on command with the other
clock input. The clock-inhibit input should be changed to the high level only while the clock input is high. A buffered,
direct clear input overrides all other inputs, including the clock, and sets all flip-flops to zero.
• Ordering Information
Inputs C 4
13 Output QH
Rev.4.00, May 10, 2006, page 1 of 7