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Renesas Electronics Components Datasheet

HD74LS166AP Datasheet

8-bit Shift Register

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HD74LS166A
8-bit Shift Register
REJ03D0450-0400
Rev.4.00
May 10, 2006
The inputs are buffered to lower the drive requirements to one series 74 or 74LS standard load, respectively. Input
clamping diodes minimize switching transients and simplify system design. This parallel in or serial-in, serial-out shift
register has a complexity of 77 equivalent gates on a monolithic chip. This device features gated clock inputs and an
overriding clear input.
The parallel-in or serial-in modes are established by the shift / load input.
When high, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock
pulse. When low, the parallel (broadside) data inputs are enabled and synchronous loading occurs on the next clock
pulse, during parallel loading, serial data flow is inhibited.
This, of course, allows the system clock to be free running and the register can be stopped on command with the other
clock input. The clock-inhibit input should be changed to the high level only while the clock input is high. A buffered,
direct clear input overrides all other inputs, including the clock, and sets all flip-flops to zero.
Features
Ordering Information
Part Name
HD74LS166AP
Package Type
DILP-16 pin
Package Code
(Previous Code)
PRDP0016AE-B
(DP-16FV)
Package
Abbreviation
P
Taping Abbreviation
(Quantity)
Pin Arrangement
Serial
Input
1
A2
B3
Parallel
Inputs C 4
D5
Clock
Inhibit
6
Clock 7
GND 8
16 VCC
15 Shift/
Load
14 Parallel
Input H
13 Output QH
12 G
11 F
10 E
Parallel
Inputs
9 Clear
(Top view)
Rev.4.00, May 10, 2006, page 1 of 7


Renesas Electronics Components Datasheet

HD74LS166AP Datasheet

8-bit Shift Register

No Preview Available !

HD74LS166A
Function Table
Clear
Shift
Load
Inputs
Clock
Inhibit
Clock
Serial
Parallel
AH
Internal outputs
QA
QB
Output
QH
L
X
X
X
X
X
L
L
L
H
X
L
L
X
X
QA0
QB0
QH0
H
L
L
X
ah
a
b
h
H
H
L
H
X
H
QAn
QGn
H
H
L
L
X
L
QAn
QGn
H
X
H
X
X
QA0
QB0
QH0
Notes: 1. H; high level, L; low level, X; irrelevant
2. ; transition from low to high level
3. a to h; the level of steady-state input at inputs A to H respectively
4. QA0 to QH0; the level of QA to QH, respectively, before the indicated steady-state input conditions were
established.
5. QAn to QGn; the level of QA to QG, respectively, before the most recent transition of the clock.
Rev.4.00, May 10, 2006, page 2 of 7


Part Number HD74LS166AP
Description 8-bit Shift Register
Maker Renesas
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HD74LS166AP Datasheet PDF






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