HD74LS166AP
features gated clock inputs and an overriding clear input.
The parallel-in or serial-in modes are established by the shift / load input.
When high, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock pulse. When low, the parallel (broadside) data inputs are enabled and synchronous loading occurs on the next clock pulse, during parallel loading, serial data flow is inhibited.
This, of course, allows the system clock to be free running and the register can be stopped on mand with the other clock input. The clock-inhibit input should be changed to the high level only while the clock input is high. A buffered, direct clear input overrides all other inputs, including the clock, and sets all flip-flops to zero.
Features
- Ordering Information
Part Name HD74LS166AP
Package Type DILP-16 pin
Package Code (Previous Code)
PRDP0016AE-B (DP-16FV)
Package Abbreviation
Taping Abbreviation (Quantity)
- Pin Arrangement
Serial...
