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ICS83056I-01 Datasheet

SINGLE-ENDED LVCMOS MULTIPLEXER

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6-BIT, 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER
ICS83056I-01
General Description
Features
The ICS83056I-01 is a 6-bit, 2:1, Single-ended
ICS
LVCMOS Multiplexer and a member of the
HiPerClockS™ HiPerClockS™ family of High Performance Clock
Solutions from IDT. The ICS83056I-01 has two
selectable single-ended LVCMOS clock inputs and
six single-ended LVCMOS clock outputs. The outputs have a VDDO
which may be set at 3.3V, 2.5V, or 1.8V, making the device ideal for
use in voltage translation applications. An output enable pin
places the output in a high impedance state which may be useful
for testing or debug. Possible applications include systems with up
to 6 transceivers which need to be independently set for different
rates. For example, a board may have six transceivers, each of
which need to be independently configured for 1 Gigabit Ethernet
or 1 Gigabit Fibre Channel rates. Another possible application may
require the ports to be independently set for FEC (Forward Error
Correction) or non-FEC rates. The device operates up to 250MHz
and is packaged in a 20 TSSOP.
Block Diagram
CLK0 Pulldown
0
Q0
CLK1 Pulldown
1
SEL0 Pulldown
6-Bit, 2:1 single-ended LVCMOS multiplexer
Maximum output frequency: 250MHz
Additive phase jitter, RMS at 155.52MHz (12kHz - 20MHz):
0.18ps (typical)
Operating supply modes:
Core/Output
VDD/VDDO
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
SEL1 Pulldown
SEL2 Pulldown
SEL3 Pulldown
SEL4 Pulldown
0
Q1
1
0
Q2
1
0
Q3
1
0
Q4
1
Pin Assignment
SEL5 1
Q5 2
VDDO 3
GND 4
Q4 5
SEL4 6
CLK1 7
VDD 8
Q3 9
SEL3 10
20 SEL0
19 Q0
18 VDDO
17 GND
16 Q1
15 SEL1
14 CLK0
13 OE
12 Q2
11 SEL2
ICS83056I-01
20-Lead TSSOP
6.50mm x 4.40mm x 0.925mm
package body
G Package
Top View
0
Q5
1
SEL5 Pulldown
OE Pullup
IDT™ / ICS™ 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER
1
ICS83056AGI-01 REV. A JANUARY 29, 2009


Renesas Electronics Components Datasheet

ICS83056I-01 Datasheet

SINGLE-ENDED LVCMOS MULTIPLEXER

No Preview Available !

ICS83056I-01
6-BIT, 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER
Table 1. Pin Descriptions
Number
1, 6
10, 11
15, 20
2, 5, 9
12, 16, 19
3, 18
4, 17
7, 14
8
13
Name
SEL5, SEL4,
SEL3, SEL2,
SEL1, SEL0
Q5, Q4, Q3,
Q2, Q1, Q0
VDDO
GND
CLK1, CLK0
VDD
OE
Type
Description
Input
Pulldown Clock select inputs. See Table 3. LVCMOS / LVTTL interface levels.
Output
Power
Power
Input
Power
Input
Pulldown
Pullup
Single-ended clock output. LVCMOS/LVTTL interface levels.
Output supply pins.
Power supply ground.
Single-ended clock inputs. LVCMOS/LVTTL interface levels.
Power supply pin.
Output enable. When LOW, outputs are in a High impedance state.
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Input Capacitance
CPD
Power Dissipation Capacitance
(per output)
RPULLUP
Input Pullup Resistor
RPULLDOWN Input Pulldown Resistor
ROUT
Output Impedance
Test Conditions
VDD = VDDO = 3.465V
VDD = VDDO = 2.625V
VDD = VDDO = 2V
VDDO = 3.465V
VDDO = 2.625V
VDDO = 2V
Minimum
Typical
4
18
19
19
51
51
15
17
25
Maximum
Units
pF
pF
pF
pF
k
k
Function Tables
Table 3. Control Input Function Table
Control Inputs
Outputs
SELx
Qx
0
CLK0
1
CLK1
IDT™ / ICS™ 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER
2
ICS83056AGI-01 REV. A JANUARY 29, 2009



Part Number ICS83056I-01
Description SINGLE-ENDED LVCMOS MULTIPLEXER
Maker Renesas
Total Page 3 Pages
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