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ICS854104 - Differential-to-LVDS Fanout Buffer

Description

The ICS854104 is a low skew, high performance 1-to-4 Differential-to-LVDS Clock Fanout Buffer.

Utilizing Low Voltage Differential Signaling (LVDS), the ICS854104 provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100.

Features

  • Four differential LVDS output pairs.
  • One differential clock input pair.
  • CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL.
  • Each output has an individual OE control.
  • Maximum output frequency: 700MHz.
  • Translates differential input signals to LVDS levels.
  • Additive phase jitter, RMS: 0.232ps (typical).
  • Output skew: 50ps (maximum).
  • Part-to-part skew: 350ps (maximum).

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Datasheet preview – ICS854104

Datasheet Details

Part number ICS854104
Manufacturer Renesas
File Size 713.74 KB
Description Differential-to-LVDS Fanout Buffer
Datasheet download datasheet ICS854104 Datasheet
Additional preview pages of the ICS854104 datasheet.

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Full PDF Text Transcription

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Low Skew, 1-to-4, Differential-to-LVDS Fanout Buffer ICS854104 DATASHEET General Description The ICS854104 is a low skew, high performance 1-to-4 Differential-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential Signaling (LVDS), the ICS854104 provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100. The ICS854104 accepts a differential input level and translates it to LVDS output levels. Guaranteed output and part-to-part skew characteristics make the ICS854104 ideal for those applications demanding well defined performance and repeatability.
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