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ICS854104 Datasheet

Differential-to-LVDS Fanout Buffer

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Low Skew, 1-to-4,
Differential-to-LVDS Fanout Buffer
ICS854104
DATASHEET
General Description
The ICS854104 is a low skew, high performance 1-to-4
Differential-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage
Differential Signaling (LVDS), the ICS854104 provides a low power,
low noise, solution for distributing clock signals over controlled
impedances of 100. The ICS854104 accepts a differential input
level and translates it to LVDS output levels.
Guaranteed output and part-to-part skew characteristics make the
ICS854104 ideal for those applications demanding well defined
performance and repeatability.
Features
Four differential LVDS output pairs
One differential clock input pair
CLK/nCLK can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, HCSL, SSTL
Each output has an individual OE control
Maximum output frequency: 700MHz
Translates differential input signals to LVDS levels
Additive phase jitter, RMS: 0.232ps (typical)
Output skew: 50ps (maximum)
Part-to-part skew: 350ps (maximum)
Propagation delay: 1.3ns (maximum)
3.3V operating supply
0°C to 70°C ambient operating temperature
Lead-free (RoHS 6) packaging
Block Diagram
CLK Pulldown
nCLK Pullup/Pulldown
Pullup
Q0
nQ0
OE0
Q1
Pullup
nQ1
OE1
Q2
Pullup
nQ2
OE2
Pullup
Q3
nQ3
OE3
Pin Assignment
OE0 1
OE1 2
OE2 3
VDD 4
GND 5
CLK 6
nCLK 7
OE3 8
16 Q0
15 nQ0
14 Q1
13 nQ1
12 Q2
11 nQ2
10 Q3
9 nQ3
ICS854104
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
ICS854104AG REVISION A JANUARY 30, 2014
1
©2014 Integrated Device Technology, Inc.


Renesas Electronics Components Datasheet

ICS854104 Datasheet

Differential-to-LVDS Fanout Buffer

No Preview Available !

ICS854104 DATASHEET
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
8
9, 10
11, 12
13, 14
15, 16
Name
OE0
OE1
OE2
VDD
GND
CLK
nCLK
OE3
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Input
Input
Input
Power
Power
Input
Input
Input
Output
Output
Output
Output
Type
Description
Pullup
Output enable pin for Q0, nQ0 outputs. See Table 3. LVCMOS/LVTTL
interface levels.
Pullup
Output enable pin for Q1, nQ1 outputs. See Table 3. LVCMOS/LVTTL
interface levels.
Pullup
Output enable pin for Q2, nQ2 outputs. See Table 3. LVCMOS/LVTTL
interface levels.
Positive supply pin.
Power supply ground.
Pulldown Non-inverting differential clock input.
Pullup/Pulldown Inverting differential clock input. VDD/2 default when left floating.
Pullup
Output enable pin for Q3, nQ3 outputs. See Table 3. LVCMOS/LVTTL
interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
RPULLUP
RPULLDOWN
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
Function Table
Table 3. Output Enable Function Table
Inputs
Outputs
OE[3:0]
Q[0:3], nQ[0:3]
0
High-Impedance
1
Active (default)
ICS854104AG REVISION A JANUARY 30, 2014
2
©2014 Integrated Device Technology, Inc.



Part Number ICS854104
Description Differential-to-LVDS Fanout Buffer
Maker Renesas
Total Page 3 Pages
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