Datasheet Details
| Part number | ICS854104 |
|---|---|
| Manufacturer | Renesas |
| File Size | 713.74 KB |
| Description | Differential-to-LVDS Fanout Buffer |
| Datasheet |
 ICS854104 Datasheet
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General Description
The ICS854104 is a low skew, high performance 1-to-4 Differential-to-LVDS Clock Fanout Buffer.
Utilizing Low Voltage Differential Signaling (LVDS), the ICS854104 provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100.
Key Features
- Four differential LVDS output pairs.
- One differential clock input pair.
- CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL.
- Each output has an individual OE control.
- Maximum output frequency: 700MHz.
- Translates differential input signals to LVDS levels.
- Additive phase jitter, RMS: 0.232ps (typical).
- Output skew: 50ps (maximum).
- Part-to-part skew: 350ps (maximum).