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ICS859S0212I Datasheet

Differential-to-LVPECL/LVDS Clock Multiplexer

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2:2, Differential-to-LVPECL/LVDS
Clock Multiplexer
ICS859S0212I
DATA SHEET
General Description
The ICS859S0212I is a 2:2 Differential-to-LVPECL/ LVDS Clock
Multiplexer which can operate up to 3GHz. The ICS859S0212I has 2
selectable differential PCLKx, nPCLKx clock inputs. The PCLKx,
nPCLKx input pairs can accept LVPECL, LVDS or CML levels. The
fully differential architecture and low propagation delay make it ideal
for use in clock distribution circuits.
Features
High speed 2:1 differential multiplexer with a 1:2 fanout buffer
Two differential LVPECL or LVDS output pairs
Two selectable differential PCLKx, nPCLKx input pairs
PCLKx, nPCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, CML
Maximum output frequency: 3GHz
Translates any single ended input signal to LVPECL levels with
resistor bias on nPCLKx input
Part-to-part skew: 100ps (maximum)
Propagation delay: 565ps (typical) at 3.3V
Additive phase jitter, RMS: 0.21ps (typical) at 3.3V
Full 3.3V or 2.5V supply modes
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
OE Pullup
CLK_SEL Pulldown
PCLK0 Pulldown
nPCLK0 Pullup/Pulldown
0
PCLK1 Pulldown
nPCLK1 Pullup/Pulldown
1
Q0
nQ0
Q1
nQ1
SEL_OUT Pullup
ICS859S0212BGI REVISION A JUNE 4, 2012
Pin Assignment
CLK_SEL 1
16 VCC
PCLK0 2
15 VEE
nPCLK0 3 14 Q0
PCLK1 4 13 nQ0
nPCLK1 5 12 Q1
nc 6 11 nQ1
OE 7
10 VEE
SEL_OUT 8
9 VCC_TAP
ICS859S0212I
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
1
©2012 Integrated Device Technology, Inc.


Renesas Electronics Components Datasheet

ICS859S0212I Datasheet

Differential-to-LVPECL/LVDS Clock Multiplexer

No Preview Available !

ICS859S0212I Data Sheet
2:2, DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER
Table 1. Pin Descriptions
Number
Name
Type
Description
1
CLK_SEL
Input
Pulldown Clock select inputs. See Table 4A. LVCMOS / LVTTL interface levels.
2
PCLK0
Input
Pulldown Non-inverting differential LVPECL clock input.
3
nPCLK0
Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. VCC/2 default when left floating.
4
PCLK1
Input
Pulldown Non-inverting differential clock input.
5
nPCLK1
Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. VCC/2 default when left floating.
6
nc
Unused
No connect.
7
OE
Input
Pullup Output enable pin. See Table 4B. LVCMOS/LVTTL interface levels.
8
SEL_OUT
Input
Pullup
Output select pin. When LOW, selects LVDS levels. When HIGH, selects LVPECL
levels. LVCMOS/LVTTL interface levels. See Table 3B.
9
10, 15
11, 12
VCC_TAP
VEE
nQ1, Q1
Power
Power
Output
Positive supply pin. See Table 3A.
Negative supply pins.
Differential output pair. LVPECL or LVDS interface levels.
13, 14
nQ0, Q0
Output
Differential output pair. LVPECL or LVDS interface levels.
16
VCC
Power
Positive supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
RPULLUP
RPULLDOWN
RVCC/2
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
RPullup/Pulldown Resistor
Test Conditions
Minimum
Typical
2
51
51
75
Maximum
Units
pF
k
k
k
ICS859S0212BGI REVISION A JUNE 4, 2012
2
©2012 Integrated Device Technology, Inc.



Part Number ICS859S0212I
Description Differential-to-LVPECL/LVDS Clock Multiplexer
Maker Renesas
Total Page 3 Pages
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