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IDT23S09E - 3.3V ZERO DELAY CLOCK BUFFER

General Description

The IDT23S09E is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications.

The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 200MHz.

Key Features

  • Phase-Lock Loop Clock Distribution.
  • 10MHz to 200MHz operating frequency.
  • Distributes one clock input to one bank of five and one bank of four outputs.
  • Separate output enable for each output bank.
  • Output Skew < 250ps.
  • Low jitter.

📥 Download Datasheet

Datasheet Details

Part number IDT23S09E
Manufacturer Renesas
File Size 196.69 KB
Description 3.3V ZERO DELAY CLOCK BUFFER
Datasheet download datasheet IDT23S09E Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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IDT23S09E 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE IDT23S09E FEATURES: • Phase-Lock Loop Clock Distribution • 10MHz to 200MHz operating frequency • Distributes one clock input to one bank of five and one bank of four outputs • Separate output enable for each output bank • Output Skew < 250ps • Low jitter <200 ps cycle-to-cycle • IDT23S09E-1 for Standard Drive • IDT23S09E-1H for High Drive • No external RC network required • Operates at 3.3V VDD • Spread spectrum compatible • Available in SOIC and TSSOP packages FUNCTIONAL BLOCK DIAGRAM DESCRIPTION: The IDT23S09E is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications.