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Renesas Electronics Components Datasheet

IDT6V31023 Datasheet

PCIE GEN1/2/3 CLOCK MULTIPLEXER

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2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER
DATASHEET
IDT6V31023
Description
The IDT6V31023 is a 2:1 differential clock mux for PCI
Express applications. It has very low additive jitter making it
suitable for use in PCIe Gen2 and Gen3 systems. The
IDT6V31023 selects between 1 of 2 differential HCSL
inputs to drive a single differential HCSL output pair. The
output can also be terminated to LVDS.
Recommended Applications
Clock muxing in PCIe Gen2 and Gen3 applications
Output Features
1 – 0.7V current mode differential HCSL output pair
Features/Benefits
Low additive jitter; suitable for use in PCIe Gen2 and
Gen3 systems
16-pin TSSOP package; small board footprint
Outputs can be terminated to LVDS; can drive a wider
variety of devices
OE control pin; greater system power management
Industrial temperature range available; supports
demanding embedded applications
Key Specifications
Additive cycle-to-cycle jitter <5 ps
Additive phase jitter (PCIe Gen3) <0.2ps
Operating frequency up to 200MHz
Block Diagram
VDD
OE
3
IN1
IN1
CLK
MUX
IN2
2 to 1
IN2
CLK
3
SEL GND
PD
Rr (IREF)
IDT® 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER
1
IDT6V31023
REV B 053112


Renesas Electronics Components Datasheet

IDT6V31023 Datasheet

PCIE GEN1/2/3 CLOCK MULTIPLEXER

No Preview Available !

IDT6V31023
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER
Pin Assignment
VDDIN 1 VDDIN 1
16 ^SEL
DIF_IN1 2
15 DIF_0
DIF_IN1 2 DIF_IN1# 3
14 DIF_0#
^PD# 4
13 GND
DIF_IN1# 3 DIF_IN2 5
DIF_IN2# 6
12 GND
11 VDD
^PD# 4 ^OE 7
GND 8
10 VDD
9 IREF
DIF_IN2 5 Note: Pins preceeded by '*^ have internal
120K ohm pull up resistors
DIF_1I6N-pin2TS#SOP6
^OE 7
GND 8
16 ^SEL Select Table
SEL OUTPUTS
0
DIF_IN2
1 D1IF5_IN1DIF_0
14 DIF_0#
13 GND
12 GND
11 VDD
10 VDD
9 IREF
Note: Pins preceeded by '*^ have internal
120K ohm pull up resistors
16-pin TSSOP
Select Table
SEL
0
1
Outputs
DIF_IN2
DIF_IN1
Pin Descriptions
PIN #
PIN NAME
1 VDDIN
2 DIF_IN1
3 DIF_IN1#
PIN TYPE
DESCRIPTION
PWR Power pin for the Inputs, nominal 3.3V
IN 0.7 V Differential TRUE input
IN 0.7 V Differential Complementary Input
4 ^PD#
Asynchronous active low input pin used to power down the device. The internal
IN
c locks are dis abled and the VCO and the crystal os c. (if any) are stopped.
5 DIF_IN2
6 DIF_IN2#
IN 0.7 V Differential TRUE input
IN 0.7 V Differential Complementary Input
7 ^OE
Activ e high input for enabling outputs. This pin has an internal pull up resistor.
IN
0 = disable outputs, 1= enable outputs
8 GND
9 IREF
10 VDD
11 VDD
12 GND
13 GND
14 DIF_0#
15 DIF_0
16 ^SEL
PWR
OUT
PWR
PWR
PWR
PWR
OUT
OUT
IN
Ground pin.
This pin establishes the reference for the differential current-mode output pairs. It
requires a fixed precision resistor to ground. 475ohm is the s tandard value for
100ohm differential impedance. Other impedances require different values. See
data sheet.
Power supply, nominal 3.3V
Power supply, nominal 3.3V
Ground pin.
Ground pin.
0.7V differential Complementary clock output
0.7V differential true clock output
Selects between one of two inputs . This pin has internal pull up resis tor.
IDT® 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER
2
IDT6V31023
REV B 053112



Part Number IDT6V31023
Description PCIE GEN1/2/3 CLOCK MULTIPLEXER
Maker Renesas
Total Page 3 Pages
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