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Renesas Electronics Components Datasheet

M5M5V5636UG-16 Datasheet

18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

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DESCRIPTION
The M5M5V5636UG is a family of 18M bit synchronous
SRAMs organized as 524288-words by 36-bit. It is designed to
eliminate dead bus cycles when turning the bus around between
reads and writes, or writes and reads. Renesas's SRAMs are
fabricated with high performance, low power CMOS technology,
providing greater reliability. M5M5V5636UG operates on 3.3V
power/ 2.5V I/O supply or a single 3.3V power supply and are
3.3V CMOS compatible.
The M5M5V5636UG also operates on a single 2.5V power
supply and is also 2.5V CMOS compatible. Therefore the
M5M5V5636UG can replace the M5M5T5636UG.
The M5M5V5636UG-16 operates at 167MHz or 133MHz and is
guaranteed both AC DC electrical characteristics of 167MHz and
those of 133MHz.
FEATURES
• Fully registered inputs and outputs for pipelined operation
• Fast clock speed: 167 and 133 MHz
• Fast access time: 3.8 and 4.2 ns
• Single 3.3V -5% and +5% power supply VDD
• Separate VDDQ for 3.3V or 2.5V I/O
• Single 2.5V -5% and +5% power supply VDD
Individual byte write (BWa# - BWd#) controls may be tied
LOW
• Single Read/Write control pin (W#)
• CKE# pin to enable clock and suspend operations
• Internally self-timed, registers outputs eliminate the need
to control G#
• Snooze mode (ZZ) for power down
• Linear or Interleaved Burst Modes
• Three chip enables for simple depth expansion
• JTAG boundary scan support
Renesas LSIs
M5M5V5636UG – 16
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
PACKAGE
165(11x15) bump BGA
Body Size (13mm x 15mm)
Bump Pitch 1.0mm
APPLICATION
High-end networking products that require high bandwidth, such
as switches and routers.
FUNCTION
Synchronous circuitry allows for precise cycle control
triggered by a positive edge clock transition.
Synchronous signals include : all Addresses, all Data Inputs,
all Chip Enables (E1#, E2, E3#), Address Advance/Load (ADV),
Clock Enable (CKE#), Byte Write Enables (BWa#, BWb#, BWc#,
BWd#) and Read/Write (W#). Write operations are controlled by
the four Byte Write Enables (BWa# - BWd#) and Read/Write(W#)
inputs. All writes are conducted with on-chip synchronous
self-timed write circuitry.
Asynchronous inputs include Output Enable (G#), Clock (CLK)
and Snooze Enable (ZZ). The HIGH input of ZZ pin puts the
SRAM in the power-down state.The Linear Burst order (LBO#) is
DC operated pin. LBO# pin will allow the choice of either an
interleaved burst, or a linear burst.
All read, write and deselect cycles are initiated by the ADV
LOW input. Subsequent burst address can be internally
generated as controlled by the ADV HIGH input.
PART NAME TABLE
M5M5V5636UG-16
Operate frequency
167MHz
133MHz
Access
3.8ns
4.2ns
1/25
Cycle
6.0ns
7.5ns
Active Current
(max.)
380mA
350mA
Standby Current
(max.)
30mA
30mA
M5M5V5636UG-16 REV.2.0


Renesas Electronics Components Datasheet

M5M5V5636UG-16 Datasheet

18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

No Preview Available !

BUMP LAYOUT(TOP VIEW)
Renesas LSIs
M5M5V5636UG – 16
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
165bump-BGA
1 2 3 4 5 6 7 8 9 10 11
A NC A7 E1# BWc# BWb# E3# CKE# ADV A17 A8 NC
B NC A6 E2 BWd# BWa# CLK W# G# A18 A9 NC
C DQPc NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPb
D DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb
E DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb
F DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb
G DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb
H MCH MCH NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ
J DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa
K DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa
L DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa
M DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa
N DQPd NC VDDQ VSS
NC
NC
MCH
VSS
VDDQ
NC DQPa
P NC
NC
A5
A3
TDI
A1
TDO
A15
A13
A11
NC
R LBO# NC
A4
A2
TMS
A0
TCK
A16
A14
A12
A10
Note1. MCH means "Must Connect High". MCH should be connected to HIGH.
2/25
M5M5V5636UG-16 REV.2.0


Part Number M5M5V5636UG-16
Description 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
Maker Renesas
Total Page 25 Pages
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