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M6MGT321S8TP - CMOS SRAM

Description

M6MGB/T321S8TP provides for Software Lock Release function.

Usually, all memory blocks are locked and can not be programed or erased, when F-WP# is low.

Using Software Lock Release function, program or erase operation 32M-bit Flash memory is a 4,194,304 bytes / 2,097,152 words, can be excuted.

Features

  • DINOR (Divided bit-line NOR) architecture for the memory cell. Access Time Flash 85ns (Max. ) 8M-bit SRAM is a 1,048,576 bytes / 524,288 words SRAM 85ns (Max. ) asynchronous SRAM fabricated by silicon-gate CMOS technology. Supply Voltage VCC=2.7 ~ 3.0V The M6MGB/T321S8TP is a Stacked micro Multi Chip Package (S- µMCP) that contents 32M-bit Flash memory and 8M-bit Static RAM in a 52-pin TSOP. M6MGB/T321S8TP is suitable for the.

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Full PDF Text Transcription (Reference)

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www.DataSheet4U.com Renesas LSIs M6MGB/T321S8TP 33,554,432-BIT (2,097,152 - WORD BY 16-BIT/4,194,304-WORD BY 8-BIT) CMOS 3.0V-ONLY FLASH MEMORY & 8,388,608-BIT (524,288-WORD BY 16-BIT/1,048,576-WORD BY 8-BIT) CMOS SRAM Stacked - µ MCP (micro Multi Chip Package) Description M6MGB/T321S8TP provides for Software Lock Release function. Usually, all memory blocks are locked and can not be programed or erased, when F-WP# is low. Using Software Lock Release function, program or erase operation 32M-bit Flash memory is a 4,194,304 bytes / 2,097,152 words, can be excuted. 3.0V-only, and high performance non-volatile memory fabricated by CMOS technology for the peripheral circuit and Features DINOR (Divided bit-line NOR) architecture for the memory cell. Access Time Flash 85ns (Max.
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