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MC100ES8111 Datasheet

1:10 Differential HSTL Clock Fanout Buffer

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Low Voltage, 1:10 Differential
®
HSTL Clock Fanout Buffer
MC100ES8111
DATASHEET
The MC100ES8111 is a bipolar monolithic differential clock fanout buffer. Designed for most
demanding clock distribution systems, the MC100ES8111 supports various applications that
require the distribution of precisely aligned differential clock signals. Using SiGe technology
and a fully differential architecture, the device offers very low skew outputs and superior digital
signal characteristics. Target applications for this clock driver are high performance clock
distribution in computing, networking and telecommunication systems.
Features
• 1:10 differential clock fanout buffer
• 80 ps maximum device skew
• SiGe technology
• Supports DC to 625 MHz operation of clock or data signals
• HSTL compatible differential clock outputs
• PECL and HSTL compatible differential clock inputs
• 3.3 V power supply for device core, 1.5 V or 1.8 V HSTL output supply
• Supports industrial temperature range
• Standard 32 lead LQFP package
• 32-lead Pb-free package available
Functional Description
The MC100ES8111 is designed for low skew clock distribution systems and supports clock
frequencies up to 625 MHz. The device accepts two clock sources. The CLK0 input accepts
HSTL compatible signals and CLK1 accepts PECL compatible signals. The selected input
signal is distributed to 10 identical, differential HSTL compatible outputs.
In order to meet the tight skew specification of the device, both outputs of a differential
output pair should be terminated, even if only one output is used. In the case where not all 10
outputs are used, the output pairs on the same package side as the parts being used on that
side should be terminated.
The HSTL compatible output levels are generated with an open emitter architecture. This
minimizes part-to-part and output-to-output skew. The open-emitter outputs require a 50 DC
termination to GND (0 V). The output supply voltage can be either 1.5 V or 1.8 V, the core
voltage supply is 3.3 V. The output enable control is synchronized internally preventing output
runt pulse generation. Outputs are only disabled or enabled when the outputs are already in
logic low state (true outputs logic low, inverted outputs logic high). The internal synchronizer
eliminates the setup and hold time requirements for the external clock enable signal. The
device is packaged in a 7x7 mm2 32-lead LQFP package.
LOW-VOLTAGE 1:10
DIFFERENTIAL
HSTL CLOCK
FANOUT BUFFER
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-04
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-04
ORDERING INFORMATION
Device
Package
MC100ES8111FA
LQFP-32
MC100ES8111FAR2
LQFP-32
MC100ES8111AC
LQFP-32 (Pb-Free)
MC100ES8111ACR2 LQFP-32 (Pb-Free)
MC100ES8111 Revision 4
1
©2009 Integrated Device Technology, Inc.


Renesas Electronics Components Datasheet

MC100ES8111 Datasheet

1:10 Differential HSTL Clock Fanout Buffer

No Preview Available !

MC100ES8111 DATASHEET
HSTL CLOCK FANOUT BUFFER
VCC
CLK0
CLK0
VCC
CLK1
CLK1
CLK_SEL
0
1
OE
Q0
Q0
Q1
Q1
24 23 22 21 20 19 18 17
Q2
VCCO
25
16
VCC0
Q2
Q3
Q2
26
15
Q7
Q3
Q2
27
Q4
14
Q7
Q4
Q1
28
13
Q8
Q5
MC100ES8111
Q5
Q1
29
12
Q8
Q6
Q0
30
Q6
11
Q9
Q7
Q0
31
Q7
10
Q9
Q8
VCCO
32
9
VCCO
Q8
12345678
Q9
Q9
OE
Figure 1. MC100ES8111 Logic Diagram
Figure 2. 23-Lead Package Pinout (Top View)
Table 1. Pin Configuration(1)
Pin
CLK0, CLK0
CLK1, CLK1
CLK_SEL
OE
Q[0-9], Q[0-9]
GND
VCC
VCCO
I/O
Input
Input
Input
Input
Output
Supply
Supply
Supply
Type
HSTL
PECL
LVCMOS
LVCMOS
HSTL
Function
Differential HSTL reference clock signal input
Differential PECL reference clock signal input
Reference clock input select
Output enable/disable. OE is synchronous to tlhe input reference clock which
eliminates possible output runt pulses when the OE state is changed.
Differential clock outputs
Negative power supply
Positive power supply of the device core (3.3 V)
Positive power supply of the HSTL outputs. All VCCO pins must be connected to the
positive power supply (1.5 V or 1.8 V) for correct DC and AC operation.
1. Input pull-up/pull-down resistors have a value of 75 k.
Table 2. Function Table
Control
Default
CLK_SEL
0
OE
0
0
1
CLK0, CLK0 (HSTL) is the active differential clock CLK1, CLK1 (PECL) is the active differential clock
input
input
Q[0-9], Q[0-9] are active. Deassertion of OE can be Q[0-9] = L, Q[0-9] =H (outputs disabled). Assertion of
asynchronous to the reference clock without
OE can be asynchronous to the reference clock
generation of output runt pulses.
without generation of output runt pulses.
MC100ES8111 Revision 4
2
©2009 Integrated Device Technology, Inc.



Part Number MC100ES8111
Description 1:10 Differential HSTL Clock Fanout Buffer
Maker Renesas
Total Page 3 Pages
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