MC100ES6014 - 2.5 V/3.3 V 1:5 Differential ECL/PECL/HSTL/LVDS Clock Driver
Pin CLK0 *, CLK0 * * CLK1 *, CLK1 * * Q0:4, Q0:4 CLK_SEL * EN * VBB VCC VEE Function ECL/PECL/HSTL CLK Input ECL/PECL/HSTL CLK Input ECL/PECL Outputs ECL/PECL Active Clock Select Input ECL Sync Enable Reference Voltage Output Positive Supply Negative Supply Table 2.
Function
Freescale Semiconductor Technical Data MC100ES6014 Rev 3, 06/2005 www.DataSheet4U.com 2.5 V/3.3 V 1:5 Differential ECL/PECL/HSTL/LVDS Clock Driver The MC100ES6014 is a low skew 1-to-5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer.
The ECL/PECL input signals can be either differential or single-ended (if the VBB output is used).
HSTL and LVDS inputs can be used when the ES6014 is operating under PECL conditions.
The ES6014 s
MC100ES6014 Features
* 25 ps Within Device Skew 400 ps Typical Propagation Delay Maximum Frequency > 2 GHz Typical The 100 Series Contains Temperature Compensation PECL and HSTL Mode: VCC = 2.375 V to 3.8 V with VEE = 0 V ECL Mode: V
