MC100ES6139 - Clock Generation Chip
Pin CLK(1), EN(1) MR(1) CLK(1) Function ECL Diff Clock Inputs ECL Sync Enable ECL Master Reset ECL Reference Output ECL Diff ÷2/4 Outputs ECL Diff ÷4/5/6 Outputs ECL Freq.
Select Input ÷2/4 ECL Freq.
Select Input ÷4/5/6 ECL Freq.
Select Input ÷4/5/6 ECL Positive Supply ECL Negative Supply 1 VCC 2
www.DataSheet4U.com Freescale Semiconductor Technical Data MC100ES6139 Rev 3, 06/2005 3.3 V ECL/PECL/HSTL/LVDS ÷2/4, ÷4/5/6 Clock Generation Chip The MC100ES6139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications.
The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned.
The device can be driven by either a differential or single-ended ECL or, if positive power supplies are us
MC100ES6139 Features
* MC100ES6139 DT SUFFIX 20-LEAD TSSOP PACKAGE CASE 948E-03 EJ SUFFIX 20-LEAD TSSOP PACKAGE Pb-FREE PACKAGE CASE 948E-03 ORDERING INFORMATION Device MC100ES6139DT MC100ES6139DTR2 MC100ES6139EJ MC100E
