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MC100ES6130

2.5/3.3V 1:4 PECL Clock Driver

MC100ES6130 Features

* a 2:1 input MUX which is ideal for redundant clock switchover applications. This device also includes a synchronous enable pin that forces the outputs into a fixed logic state. Enable or disable state is initiated only after the outputs are in a LOW state to eliminate the possibility of a runt clock

MC100ES6130 General Description

Number 1, 2, 3, 4, 5, 6, 7, 8 9 10 Name Q0 to Q3 Q0 to Q3 VEE IN_SEL Description LVPECL differential outputs: Terminate with 50Ω to VCC

*2V. For single-ended applications, terminate the unused output with 50Ω to VCC

*2V. Negative power supply: For LVPECL applications, connect to GND. L.

MC100ES6130 Datasheet (342.63 KB)

Preview of MC100ES6130 PDF

Datasheet Details

Part number:

MC100ES6130

Manufacturer:

Motorola

File Size:

342.63 KB

Description:

2.5/3.3v 1:4 pecl clock driver.
www.DataSheet4U.com Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order number: MC100ES6130 Rev 1, 5/2004 2.5/3.3V 1:4 PECL Cl.

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TAGS

MC100ES6130 2.5 3.3V PECL Clock Driver Motorola

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