MC100ES6039 - 3.3V ECL/PECL/HSTL/LVDS Generation Chip
Pin CLK(1), CLK(1) EN(1) MR(1) www.DataSheet4U.com Function ECL Diff Clock Inputs ECL Sync Enable ECL Master Reset ECL Reference Output ECL Diff ÷2/4 Outputs ECL Diff ÷4/6 Outputs ECL Freq.
Select Input ÷2/4 ECL Freq.
Select Input ÷4/6 ECL Positive Supply ECL Negative Supply No Connect 1 VCC 2 EN
Freescale Semiconductor Technical Data MC100ES6039 Rev 2, 06/2005 www.DataSheet4U.com 3.3 V ECL/PECL/HSTL/LVDS ÷2/4, ÷4/6 Clock Generation Chip The MC100ES6039 is a low skew ÷2/4, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications.
The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned.
The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, L
MC100ES6039 Features
* Maximum Frequency >1.0 GHz Typical 50 ps Output-to-Output Skew PECL Mode Operating Range: VCC = 3.135 V to 3.8 V with VEE = 0 V ECL Mode Operating Range: VCC = 0 V with VEE =
* 3.135 V to
