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Renesas Electronics Components Datasheet

NP45N06VUK Datasheet

N-channel Power MOS FET

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Preliminary Data Sheet
NP45N06VUK, NP45N06PUK
60 V – 45 A – N-channel Power MOS FET
Application: Automotive
R07DS0953EJ0100
Rev.1.00
Nov 20, 2012
Description
These products are N-channel MOS Field Effect Transistors designed for high current switching applications.
Features
Super low on-state resistance
RDS(on) = 9.6 mMAX. (VGS = 10 V, ID = 23 A)
Low Ciss: Ciss = 1690 pF TYP. (VDS = 25 V)
Designed for automotive application and AEC-Q101 qualified
Ordering Information
Part No.
NP45N06VUK-E1-AY *1
NP45N06VUK-E2-AY *1
NP45N06PUK-E1-AY *1
NP45N06PUK-E2-AY *1
Lead Plating
Pure Sn (Tin)
Packing
Tape 2500 p/reel
Taping (E1 type)
Taping (E2 type)
Tape 800 p/reel
Taping (E1 type)
Taping (E2 type)
Note: *1 Pb-free (This product does not contain Pb in the external electrode)
Package
TO-252 (MP-3ZP)
TO-263 (MP-25ZP)
Absolute Maximum Ratings (TA = 25°C)
Item
Symbol
Drain to Source Voltage (VGS = 0 V)
VDSS
Gate to Source Voltage (VDS = 0 V)
VGSS
Drain Current (DC) (TC = 25°C)
Drain Current (pulse) *1
ID(DC)
ID(pulse)
Total Power Dissipation (TC = 25°C)
PT1
Total Power Dissipation
(TA = 25°C)
NP45N06VUK
NP45N06PUK
PT2
Channel Temperature
Tch
Storage Temperature
Repetitive Avalanche Current *2
Repetitive Avalanche Energy *2
Tstg
IAR
EAR
Notes: *1 TC = 25°C, PW 10 s, Duty Cycle 1%
*2 RG = 25 , VGS = 20 V 0 V
Ratings
60
20
45
135
75
1.2
1.8
175
–55 to +175
19
36
Unit
V
V
A
A
W
W
W
°C
°C
A
mJ
Thermal Resistance
Channel to Case Thermal Resistance
Channel to Ambient Thermal Resistance
Rth(ch-C)
Rth(ch-A)
NP45N06VUK
NP45N06PUK
2.00 °C/W
125 °C/W
83.3 °C/W
R07DS0953EJ0100 Rev.1.00
Nov 20, 2012
Page 1 of 8


Renesas Electronics Components Datasheet

NP45N06VUK Datasheet

N-channel Power MOS FET

No Preview Available !

NP45N06VUK, NP45N06PUK
Electrical Characteristics (TA = 25°C)
Item
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate to Source Threshold Voltage
Forward Transfer Admittance *1
Drain to Source On-state Resistance *1
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage *1
Reverse Recovery Time
Reverse Recovery Charge
Note: *1 Pulsed test
Symbol
IDSS
IGSS
VGS(th)
| yfs |
RDS(on)
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QG
QGS
QGD
VF(S-D)
trr
Qrr
MIN.
2.0
17
TYP.
3.0
34
7.8
1690
155
70
15
5
37
3
30
8
8
0.9
32
35
MAX.
1
100
4.0
9.6
2540
240
130
40
20
80
10
45
1.5
Unit
A
nA
V
S
m
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
Test Conditions
VDS = 60 V, VGS = 0 V
VGS = 20 V, VDS = 0 V
VDS = VGS, ID = 250 A
VDS = 5 V, ID = 23 A
VGS = 10 V, ID = 23 A
VDS = 25 V
VGS = 0 V
f = 1 MHz
VDD = 30 V, ID = 23 A
VGS = 10 V
RG = 0
VDD = 48 V
VGS = 10 V
ID = 45 A
IF = 45 A, VGS = 0 V
IF = 45 A, VGS = 0 V
di/dt = 100 A/s
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
PG.
VGS = 20 0 V
50 Ω
L
VDD
BVDSS
ID
VDD
IAS
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
IG = 2 mA
PG. 50 Ω
RL
VDD
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
PG. RG
VGS
0
τ
τ = 1 μs
Duty Cycle 1%
RL
VGS
VGS
Wave Form
10%
0
VDD
VDS
90%
VDS
VDS
Wave Form
0
td(on)
VGS 90%
90%
10% 10%
tr td(off)
tf
ton toff
R07DS0953EJ0100 Rev.1.00
Nov 20, 2012
Page 2 of 8


Part Number NP45N06VUK
Description N-channel Power MOS FET
Maker Renesas
Total Page 10 Pages
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