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R1QBA3618CBG - 36-Mbit DDRII+ SRAM

Download the R1QBA3618CBG datasheet PDF. This datasheet also covers the R1QBA3636CBG variant, as both devices belong to the same 36-mbit ddrii+ sram family and are provided as variant models within a single manufacturer datasheet.

Description

The R1Q#A3636 is a 1,048,576-word by 36-bit and the R1Q#A3618 is a 2,097,152-word by 18-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.

It integrates unique synchronous peripheral circuitry and a burst counter.

Features

  • ႑ Power Supply.
  • 1.8 V for core (VDD), 1.4 V to VDD for I/O (VDDQ) ႑ Clock.
  • Fast clock cycle time for high bandwidth.
  • Two input clocks (K and /K) for precise DDR timing at clock rising edges only.
  • Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems.
  • Clock-stop capability with Ps restart ႑ I/O.
  • Common data input/output bus.
  • Pipelined double data rate operation.
  • HSTL I/O.
  • User programmable o.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (R1QBA3636CBG-Renesas.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
R1QBA36**CB* / R1QEA36**CB* Series R1QBA3636CBG / R1QBA3618CBG / R1QBA3609CBG R1QEA3636CBG / R1QEA3618CBG / R1QEA3609CBG R1QHA3636CBG / R1QHA3618CBG / R1QHA3609CBG R1QLA3636CBG / R1QLA3618CBG / R1QLA3609CBG 36-Mbit DDRII+ SRAM 2-word Burst R10DS0159EJ0009 Rev. 0.09a 2011.09.14 Description The R1Q#A3636 is a 1,048,576-word by 36-bit and the R1Q#A3618 is a 2,097,152-word by 18-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K.
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