R1QBA3618CBG Datasheet | Renesas

R1QBA36- - CB- / R1QEA36- - CB- Series R1QBA3636CBG / R1QBA3618CBG / R1QBA3609CBG R1QEA3636CBG / R1QEA3618CBG / R1QEA3609CBG R1QHA3636CBG / R1QHA3618CBG / R1QHA3609CBG R1QLA3636CBG / R1QLA3618CBG / R1QLA3609CBG 36-Mbit DDRII+ SRAM 2-word Burst R10DS0159EJ0009 Rev. 0.09a 2011.09.14 Description The R1Q#A3636 is a 1,048,576-word by 36-bit and the R1Q#A3618 is a 2,097,152-word by 18-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration. These products are packaged in 165-pin plastic FBGA package. # = B: Latency =2.5, w/o ODT # = E: Latency =2.5, w/ ODT # = H: Latency =2.0, w/o ODT # = L: Latency =2.0, w/ ODT Features ႑ Power Supply - 1.8 V for core (VDD), 1.4 V to VDD for I/O (VDDQ) ႑ Clock - Fast clock cycle time for high bandwidth - Two input clocks (K and /K) for precise DDR timing at clock rising edges only - Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems - Clock-stop capability with Ps restart ႑ I/O - mon data input/output bus - Pipelined double data rate operation - HSTL I/O - User programmable output impedance - DLL/PLL circuitry for wide output data valid window and future frequency scaling - Data valid pin (QVLD) to indicate valid data on the output ႑ Function - Two-tick burst for low DDR transaction size - Internally self-timed write control - Simple control logic for easy depth...