CY7C1371D (Cypress Semiconductor)
18-Mbit (512 K x 36/1 M x 18) Flow-Through SRAM
CY7C1371D CY7C1373D
18-Mbit (512 K × 36/1 M × 18) Flow-Through SRAM with NoBL™ Architecture
18-Mbit (512 K × 36/1 M × 18) Flow-through SRAM with NoBL
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17 views
CY7C1370KV25 (Cypress Semiconductor)
18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1370KV25 CY7C1372KV25
18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Architecture
18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Ar
Published:
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16 views
CY7C1372KV25 (Cypress Semiconductor)
18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1370KV25 CY7C1372KV25
18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Architecture
18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Ar
Published:
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16 views
CY7C1372KV33 (Cypress Semiconductor)
18-Mbit (512K x 36/1M x 18) Pipelined SRAM
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15 views
CY7C1370KV33 (Cypress Semiconductor)
18-Mbit (512K x 36/1M x 18) Pipelined SRAM
Published:
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15 views
CY7C1370KVE33 (Cypress Semiconductor)
18-Mbit (512K x 36/1M x 18) Pipelined SRAM
Published:
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14 views
CY7C1420AV18 (Cypress Semiconductor)
(CY7C14xxAV18) 36-Mbit DDR-II SRAM 2-Word Burst Architecture
www.DataSheet4U.com
PRELIMINARY
CY7C1416AV18 CY7C1427AV18 CY7C1418AV18 CY7C1420AV18
36-Mbit DDR-II SRAM 2-Word Burst Architecture
Features
• 36-Mbi
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14 views
CY7C1372KVE33 (Cypress Semiconductor)
18-Mbit (512K x 36/1M x 18) Pipelined SRAM
Published:
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13 views
CY7C1371KV33 (Cypress Semiconductor)
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1371KV33 CY7C1371KVE33
CY7C1373KV33
18-Mbit (512K × 36/1M × 18) Flow-Through SRAM with NoBL™ Architecture (With ECC)
18-Mbit (512K × 36/1M × 18)
Published:
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13 views
CY7C1371KVE33 (Cypress Semiconductor)
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1371KV33 CY7C1371KVE33
CY7C1373KV33
18-Mbit (512K × 36/1M × 18) Flow-Through SRAM with NoBL™ Architecture (With ECC)
18-Mbit (512K × 36/1M × 18)
Published:
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13 views
CY7C1270KV18 (Cypress Semiconductor)
36-Mbit DDR II+ SRAM Two-Word Burst Architecture
CY7C1268KV18/CY7C1270KV18
36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
36-Mbit DDR II+ SRAM Two-Word Burst Architecture
Published:
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13 views
CY7C1372D (Cypress)
18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM
CY7C1370D CY7C1372D
18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture
18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Arch
Published:
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13 views
CY7C1411AV18 (Cypress Semiconductor)
(CY7C14xxAV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1411AV18, CY7C1426AV18 www.DataSheet4U.com CY7C1413AV18, CY7C1415AV18
36-Mbit QDR™-II SRAM 4-Word Burst Architecture
Features
■
Functional Descr
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13 views
CY7C1372DV25 (Cypress Semiconductor)
18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1370DV25 CY7C1372DV25
18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Architecture
18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Ar
Published:
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13 views
CY7C1470V25 (Cypress Semiconductor)
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM
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12 views
CY7C1217F (Cypress Semiconductor)
1-Mbit (32K x 36) Flow-Through Sync SRAM
CY7C1217F
www.DataSheet4U.com
1-Mbit (32K x 36) Flow-Through Sync SRAM
Features
• 32K x 36 common I/O • 3.3V –5% and +10% core power supply (VDD) • 3
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12 views
CY7C1363C (Cypress Semiconductor)
(CY7C1361C / CY7C1363C) 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
PRELIMINARY
CY7C1361C CY7C1363C
9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
Features
• Supports 133-MHz bus operations • 256K × 36/512K × 18 comm
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12 views
CY7C12431KV18 (Cypress Semiconductor)
36-Mbit QDR II SRAM 4-Word Burst Architecture
36-Mbit QDR II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C
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12 views
CY7C1241KV18 (Cypress Semiconductor)
36-Mbit QDR II SRAM 4-Word Burst Architecture
36-Mbit QDR II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C
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12 views
CY7C1243V18 (Cypress Semiconductor)
36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1241V18 CY7C1256V18 CY7C1243V18 CY7C1245V18
36-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
Features
• Separate independ
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12 views
