.
AHA4501 - 36 Mbits/sec Turbo Product Code Encoder/Decoder
CY7C1371KV33 - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CYF0036V - 18/36/72 Mbit Programmable FIFOs Master reset to clear entire FIFO
CY7C1367C - 9-Mbit Pipelined DCD Sync SRAM
CY7C1423KV18 - 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture
CY7C1380S - 18-Mbit (512 K x 36/1 M x 18) Pipelined SRAM
CY7C1372KVE33 - 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1472BV33 - 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM
CY7C1474BV33 - 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM
CY7C1263XV18 - 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture
M36L0R7050 - 128 Mbit (Multiple Bank / Multi-Level / Burst) Flash Memory 32 Mbit (2M x16) PSRAM
CY7C1474BV25 - (CY7C147xBV25) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM
CY7C1426AV18 - (CY7C14xxAV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1426BV18 - (CY7C14xxBV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1422AV18 - 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1371S - 18-Mbit (512K x 36) Flow-Through SRAM
CY7C1447AV25 - 36-Mbit Flow-Through SRAM
CY7C1354CV25 - 9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1371KVE33 - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1463KV33 - 36-Mbit (1M x 36/2M x 18) Flow-Through SRAM