* Pin compatible and functionally equivalent to ZBT
* Supports 250 MHz bus operations with zero wait states
* Available speed grades are 250, 200 and 167 MHz
* Internally self timed output buffer control to eliminate the need to use asynchronous OE
* Fully registered (inputs and
CY7C1462AV33 Datasheet (833.98 KB)
CY7C1462AV33
Cypress Semiconductor
833.98 KB
(cy7c146xav33) 36-mbit pipelined sram.
CY7C1460AV33 CY7C1462AV33 36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture 36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Archit.
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